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Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

  • Uwe Meyer-Bäse
  • Hariharan Natarajan
  • Andrew G Dempster
Open Access
Research Article

Abstract

It has recently been shown that thse Open image in new window -dimensional reduced adder graph (RAG- Open image in new window ) technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG- Open image in new window technique can be applied to these algorithms. This RAG- Open image in new window DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp- Open image in new window algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

Keywords

Fourier Fourier Transform Information Technology Quantum Information Data Flow 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Heideman MT, Johnson DH, Burrus CS: Gauss and the history of the fast Fourier transform. IEEE Acoustic Speech & Signal Processing Magazine 1984,1(4):14-21.Google Scholar
  2. 2.
    Burrus CS: Index mappings for multidimensional formulation of the DFT and convolution. IEEE Transactions on Acoustics, Speech, and Signal Processing 1977,25(3):239-242. 10.1109/TASSP.1977.1162938CrossRefMATHGoogle Scholar
  3. 3.
    Macleod MD: Multiplierless implementation of rotators and FFTs. EURASIP Journal on Applied Signal Processing 2005,2005(17):2903-2910. 10.1155/ASP.2005.2903CrossRefMATHGoogle Scholar
  4. 4.
    Altera Corporation : FFT: MegaCore Function User Guide. Ver. 2.1.3, 2004Google Scholar
  5. 5.
    Xilinx Corporation : Fast Fourier Transform. LogiCore v3.1, November 2004Google Scholar
  6. 6.
    Baas B: SPIFFEE: an energy-efficient single-chip 1024-point FFT processor. 1998.http://nova.stanford.edu/~bbaas/fftinfo.htmlGoogle Scholar
  7. 7.
    Sunada G, Jin J, Berzins M, Chen T: COBRA: an 1.2 million transistor expandable column FFT chip. Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '94), October 1994, Cambridge, Mass, USA 546-550.Google Scholar
  8. 8.
    Texas Memory Systems : TM-66 swifft chip. 1996.http://www.texmemsys.comGoogle Scholar
  9. 9.
    SHARP Microeletronics : Bdsp9124 digital signal processor. 1997.http://www.butterflydsp.comGoogle Scholar
  10. 10.
    Lavoie P: A high-speed CMOS implementation of the Winograd Fourier transform algorithm. IEEE Transactions on Signal Processing 1996,44(8):2121-2126. 10.1109/78.533738MathSciNetCrossRefGoogle Scholar
  11. 11.
    Panneerselvam G, Graumann P, Turner L: Implementation of fast Fourier transforms and discrete cosine transforms in FPGAs. Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications (FPL '95), August-September 1995, Oxford, UK, Lecture Notes in Computer Science 975: 272-281.CrossRefGoogle Scholar
  12. 12.
    Goslin G: Using Xilinx FPGAs to design custom digital signal processing devices. Proceedings of the DSPX, January 1995 565-604.Google Scholar
  13. 13.
    Shirazi N, Athanas PM, Abbott AL: Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine. Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications (FPL '95), August-September 1995, Oxford, UK, Lecture Notes in Computer Science 975: 282-292.CrossRefGoogle Scholar
  14. 14.
    Dick C: Computing 2-D DFTs using FPGAs. Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers (FPL '96), September 1996, Darmstadt, Germany, Lecture Notes in Computer Science 1142: 96-105.CrossRefGoogle Scholar
  15. 15.
    Bull DR, Horrocks DH: Reduced-complexity digital filtering structures using primitive operations. Electronics Letters 1987,23(15):769-771. 10.1049/el:19870546CrossRefGoogle Scholar
  16. 16.
    Bull DR, Horrocks DH: Primitive operator digital filters. IEE Proceedings G: Circuits, Devices and Systems 1991,138(3):401-412. 10.1049/ip-g-2.1991.0066Google Scholar
  17. 17.
    Dempster AG, Macleod MD: Constant integer multiplication using minimum adders. IEE Proceedings: Circuits, Devices and Systems 1994,141(5):407-413. 10.1049/ip-cds:19941191MATHGoogle Scholar
  18. 18.
    Dempster AG, Macleod MD: Comments on "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1998,45(2):242-243. 10.1109/82.661661CrossRefGoogle Scholar
  19. 19.
    Gustafsson O, Dempster AG, Wanhammar L: Extended results for minimum-adder constant integer multipliers. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '02), May 2002, Phoenix, Ariz, USA 1: 73-76.Google Scholar
  20. 20.
    Dempster AG, Macleod MD: Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1995,42(9):569-577. 10.1109/82.466647CrossRefMATHGoogle Scholar
  21. 21.
    Hartley RT: Subexpression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1996,43(10):677-688. 10.1109/82.539000CrossRefGoogle Scholar
  22. 22.
    Macleod MD, Dempster AG: Multiplierless FIR filter design algorithms. IEEE Signal Processing Letters 2005,12(3):186-189.CrossRefGoogle Scholar
  23. 23.
    Stearns SD, Hush DR: Digital Signal Analysis. Prentice-Hall, Englewood Cliffs, NJ, USA; 1990.Google Scholar
  24. 24.
    Oppenheim AV, Schafer RW: Discrete-Time Signal Processing. Prentice-Hall, Englewood Cliffs, NJ, USA; 1992.Google Scholar
  25. 25.
    Brigham E: FFT. 3rd edition. Oldenbourg, München, Germany; 1987.MATHGoogle Scholar
  26. 26.
    Ramirez R: The FFT: Fundamentals and Concepts. Prentice-Hall, Englewood Cliffs, NJ, USA; 1985.Google Scholar
  27. 27.
    Burrus C, Parks T: DFT/FFT and Convolution Algorithms. John Wiley & Sons, New York, NY, USA; 1985.Google Scholar
  28. 28.
    Elliott D, Rao K: Fast Transforms Algorithms, Analyses, Applications. Academic Press, New York, NY, USA; 1982.MATHGoogle Scholar
  29. 29.
    Nussbaumer H: Fast Fourier Transform and Convolution Algorithms. Springer, Heidelberg, Germany; 1990.Google Scholar
  30. 30.
    Rader C: Discrete Fourier transform when the number of data samples is prime. Proceedings of the IEEE 1968,56(6):1107-1108.CrossRefGoogle Scholar
  31. 31.
    McClellan J, Rader C: Number Theory in Digital Signal Processing. Prentice-Hall, Englewood Cliffs, NJ, USA; 1979.MATHGoogle Scholar
  32. 32.
    Narasimha M, Shenoi K, Peterson A: Quadratic residues: application to chirp filters and discrete Fourier transforms. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '76), April 1976, Philadelphia, Pa, USA 1: 376-378.CrossRefGoogle Scholar
  33. 33.
    Meyer-Bäse U, Sunkara D, Castillo E, Garcia A: Custom instruction set NIOS-based OFDM processor for FPGAs. Wireless Sensing and Processing, April 2006, Kissimmee, Fla, USA, Proceedings of SPIE 6248: article number 62480OCrossRefGoogle Scholar
  34. 34.
    Macleod MD, Dempster AG: Common subexpression elimination algorithm for low-cost multiplierless implementation of matrix multipliers. Electronics Letters 2004,40(11):651-652. 10.1049/el:20040436CrossRefGoogle Scholar
  35. 35.
    Gorman SF, Wills JM: Partial column FFT pipelines. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 1995,42(6):414-423. 10.1109/82.392316CrossRefMATHGoogle Scholar
  36. 36.
    Gustafsson O, Dempster AG, Wanhammar L: Multiplier blocks using carry-save adders. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004, Vancouver, BC, Canada 2: 473-476.Google Scholar
  37. 37.
    White SA: Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE Transactions on Acoustics, Speech and Signal Processing Magazine 1989,6(3):4-19.Google Scholar
  38. 38.
    Soderstrand M, Jenkins W, Jullien G, Taylor F: Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press Reprint Series. IEEE Press, New York, NY, USA; 1986.Google Scholar
  39. 39.
    Voronenko Y, Püschel M: Multiplierless multiple constant multiplication. to appear in ACM Transactions on AlgorithmsGoogle Scholar
  40. 40.
    Gustafsson O: A difference based adder graph heuristic for multiple constant multiplication problems. Proceedings Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '07), May 2007, New Orleans, La, USA submittedGoogle Scholar
  41. 41.
    Welch P: A fixed-point fast Fourier transform error analysis. IEEE Transactions on Audio and Electroacoustics 1969,17(2):151-157. 10.1109/TAU.1969.1162035CrossRefGoogle Scholar

Copyright information

© Meyer-Bäse et al. 2007

Authors and Affiliations

  • Uwe Meyer-Bäse
    • 1
  • Hariharan Natarajan
    • 1
  • Andrew G Dempster
    • 2
  1. 1.Department of Electrical and Computer EngineeringFlorida State UniversityTallahasseeUSA
  2. 2.School of Surveying and Spatial Information SystemsUniversity of New South WalesSydneyAustralia

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