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Optimum Wordlength Search Using Sensitivity Information

  • Kyungtae HanEmail author
  • Brian L. Evans
Open Access
Research Article
First Online:
Part of the following topical collections:
  1. Design Methods for DSP Systems

Abstract

Many digital signal processing algorithms are first developed in floating point and later converted into fixed point for digital hardware implementation. During this conversion, more than 50% of the design time may be spent for complex designs, and optimum wordlengths are searched by trading off hardware complexity for arithmetic precision at system outputs. We propose a fast algorithm for searching for an optimum wordlength. This algorithm uses sensitivity information of hardware complexity and system output error with respect to the signal wordlengths, while other approaches use only one of the two sensitivities. This paper presents various optimization methods, and compares sensitivity search methods. Wordlength design case studies for a wireless demodulator show that the proposed method can find an optimum solution in one fourth of the time that the local search method takes. In addition, the optimum wordlength searched by the proposed method yields 30% lower hardware implementation costs than the sequential search method in wireless demodulators. Case studies demonstrate the proposed method is robust for searching for the optimum wordlength in a nonconvex space.

Keywords

Search Method Digital Signal Processing System Output Hardware Implementation Sensitivity Information 
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References

  1. 1.
    Keding H, Willems M, Coors M, Meyr H: FRIDGE: A fixed-point design and simulation environment. Proceedings of IEEE Design, Automation and Test in Europe (DATE '98), February 1998, Paris, France 429–435.CrossRefGoogle Scholar
  2. 2.
    Oppenheim AV, Schafer RW, Buck JR: Discrete-Time Signal Processing. Prentice-Hall, Upper Saddle River, NJ, USA; 1998.Google Scholar
  3. 3.
    Choi H, Burleson WP: Search-based wordlength optimization for VLSI/DSP synthesis. Proceedings of IEEE Workshop on VLSI Signal Processing, VII, October 1994, La Jolla, Calif, USA 198–207.Google Scholar
  4. 4.
    Sung W, Kum K-I: Simulation-based word-length optimization method for fixed-point digital signal processing systems. IEEE Transactions on Signal Processing 1995, 43(12):3087–3090. 10.1109/78.476465CrossRefGoogle Scholar
  5. 5.
    Han K, Eo I, Kim K, Cho H: Numerical word-length optimization for CDMA demodulator. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '01), May 2001, Sydney, NSW, Australia 4: 290–293.Google Scholar
  6. 6.
    Cantin M-A, Savaria Y, Prodanos D, Lavoie P: An automatic word length determination method. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '01), May 2001, Sydney, NSW, Australia 5: 53–56.Google Scholar
  7. 7.
    Han K, Evans BL: Wordlength optimization with complexity-and-distortion measure and its application to broadband wireless demodulator design. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '04), May 2004, Montreal, Quebec, Canada 5: 37–40.Google Scholar
  8. 8.
    Wadekar SA, Parker AC: Accuracy sensitive word-length selection for algorithm optimization. Proceedings of International Conference on Computer Design: VLSI in Computers and Processors (ICCD '98), October 1998, Austin, Tex, USA 54–61.Google Scholar
  9. 9.
    Constantinides GA, Cheung PYK, Luk W: Wordlength optimization for linear digital signal processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2003, 22(10):1432–1442. 10.1109/TCAD.2003.818119CrossRefGoogle Scholar
  10. 10.
    Cmar R, Rijnders L, Schaumont P, Vernalde S, Bolsens I: A methodology and design environment for DSP ASIC fixed point refinement. Proceedings of Design, Automation and Test in Europe Conference and Exhibition, March 1999, Munich, Germany 271–276.Google Scholar
  11. 11.
    Stephenson M, Babb J, Amarasinghe S: Bidwidth analysis with application to silicon compilation. Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation , June 2000, Vancouver, BC, Canada 108–120.Google Scholar
  12. 12.
    Shi C, Brodersen RW: Automated fixed-point data-type optimization tool for signal processing and communication systems. Proceedings of 41st Design Automation Conference, June 2004, San Diego, Calif, USA 478–483.Google Scholar
  13. 13.
    Kim S, Kum K-I, Sung W: Fixed-point optimization utility for C and C++ based digital signal processing programs. IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing 1998, 45(11):1455–1464. 10.1109/82.735357CrossRefGoogle Scholar
  14. 14.
    Kum K-I, Sung W: Combined word-length optimization and high-level synthesis of digital signal processing systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2001, 20(8):921–930. 10.1109/43.936374CrossRefGoogle Scholar
  15. 15.
    Nayak A, Haldar M, Choudhary A, Banerjee P: Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. Proceedings of Design, Automation and Test in Europe (DATE '01), March 2001, Munich, Germany 722–728.Google Scholar
  16. 16.
    Cantin M-A, Savaria Y, Lavoie P: A comparison of automatic word length optimization procedures. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '02), May 2002, Phoenix-Scottsdale, Ariz, USA 2: 612–615.Google Scholar
  17. 17.
    SystemC 2.0 User's Guide 2002, [online], available: https://doi.org/www.systemc.org
  18. 18.
    Kim S, Sung W: A floating-point to fixed-point assembly program translator for the TMS 320C25. IEEE Transactions on Circuits and SystemsPart II: Analog and Digital Signal Processing 1994, 41(11):730–739. 10.1109/82.331543Google Scholar
  19. 19.
    Rosen KH: Handbook of Discrete and Combinatorial Mathematics. CRC Press, Boca Raton, Fla, USA; 2000.zbMATHGoogle Scholar
  20. 20.
    Beveridge GSG, Schechter RS: Optimization: Theory and Practice. McGraw-Hill, New York, NY, USA; 1970.zbMATHGoogle Scholar
  21. 21.
    Wepman JA: Analog-to-digital converters and their applications in radio receivers. IEEE Communications Magazine 1995, 33(5):39–45. 10.1109/35.393000CrossRefGoogle Scholar
  22. 22.
    Nahm S, Han K, Sung W: A CORDIC-based digital quadrature mixer: comparison with a ROM-based architecture. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '98), May–June 1998, Monterey, Calif, USA 4: 385–388.Google Scholar
  23. 23.
    Han K, Eo I, Kim K, Cho H: Bit constraint parameter decision method for CDMA digital demodulator. Proceedings of 5th CDMA International Conference and Exhibition, November 2000, Seoul, Korea 2: 583–586.Google Scholar
  24. 24.
    Wu J-S, Liou M-L, Ma H-P, Chiueh T-D: A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]. IEEE Journal of Solid-State Circuits 1997, 32(10):1499–1510. 10.1109/4.634658CrossRefGoogle Scholar
  25. 25.
    Fiore PD, Lee L: Closed-form and real-time wordlength adaptation. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '99), March 1999, Phoenix, Ariz, USA 4: 1897–1900.Google Scholar
  26. 26.
    Bolcskei H, Paulraj AJ, Hari KVS, Nabar RU, Lu WW: Fixed broadband wireless access: state of the art, challenges, and future directions. IEEE Communications Magazine 2001, 39(1):100–108. 10.1109/35.894383CrossRefGoogle Scholar
  27. 27.
    Erceg V, Hari KVS, Smith MS, et al.: Channel models for fixed wireless applications. in IEEE 802.16. proposal 802.16.3c-01/29, 2001Google Scholar
  28. 28.
    Baum DS: Simulating the SUI channel models. Information Systems Laboratory, Stanford University, Stanford, Calif, USA; 2001.Google Scholar
  29. 29.
    Shim B, Shanbhag N: Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. IEEE Transactions on Signal Processing 2003, 51(1):282–292. 10.1109/TSP.2002.806583CrossRefGoogle Scholar
  30. 30.
    Constantinides GA: High level synthesis and word length optimization of digital signal processing systems, Ph.D. dissertation. Department of Electronic & Electrical Engineering, University College London, London, UK; 2001.Google Scholar
  31. 31.
    Fletcher R: Practical Methods of Optimization, Vol. 2: Constrained Optimization. John Wiley & Sons, New York, NY, USA; 1981.zbMATHGoogle Scholar
  32. 32.
    Hayes MH: Statistical Digital Signal Processing and Modeling. John Wiley & Sons, New York, NY, USA; 1996.Google Scholar

Copyright information

© K. Han and B. L. Evans. 2006

This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Authors and Affiliations

  1. 1.Embedded Signal Processing Laboratory, Wireless Networking and Communications GroupThe University of Texas at AustinAustinUSA

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