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Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

  • Veselin N. IvanovićEmail author
  • Radovan Stojanović
  • L Jubivša Stanković
Open Access
Research Article
Part of the following topical collections:
  1. Design Methods for DSP Systems

Abstract

Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized by using the proposed architecture: (i) the spectrogram (SPEC) and the pseudo-Wigner distribution (WD), as the oldest and the most important tools used in TF signal analysis; (ii) the S-method (SM) with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT) realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA) chips. Also, at the implementation (silicon) level, it has been compared with the single-cycle implementation (SCI) architecture.

Keywords

Silicon Fourier Fourier Transformation Information Technology Convolution 

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Copyright information

© Ivanović et al. 2006

Authors and Affiliations

  • Veselin N. Ivanović
    • 1
    Email author
  • Radovan Stojanović
    • 1
  • L Jubivša Stanković
    • 1
  1. 1.Department of Electrical EngineeringUniversity of MontenegroPodgoricaSerbia and Montenegro

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