FPGA Prototyping of RNN Decoder for Convolutional Codes

  • Zoran SalcicEmail author
  • Stevan Berber
  • Paul Secker
Open Access
Research Article


This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.


Activation Function Quantum Information Communication Channel Design Specification Design Methodology 


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Copyright information

© Salcic et al. 2006

Authors and Affiliations

  1. 1.Department of Electrical and Electronic Engineeringthe University of AucklandAucklandNew Zealand

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