The European Physical Journal Special Topics

, Volume 228, Issue 10, pp 2269–2285 | Cite as

Sklansky tree adder realization in 1S1R resistive switching memory architecture

  • Anne SiemonEmail author
  • Stephan Menzel
  • Debjyoti Bhattacharjee
  • Rainer Waser
  • Anupam Chattopadhyay
  • Eike Linn
Regular Article
Part of the following topical collections:
  1. Memristor-based Systems: Nonlinearity, Dynamics and Applications


Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed.


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Copyright information

© EDP Sciences, Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Anne Siemon
    • 1
    • 2
    Email author
  • Stephan Menzel
    • 2
    • 3
  • Debjyoti Bhattacharjee
    • 4
  • Rainer Waser
    • 1
    • 2
    • 3
  • Anupam Chattopadhyay
    • 4
  • Eike Linn
    • 1
    • 2
  1. 1.Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen UniversityAachenGermany
  2. 2.JARA – Fundamentals for Future Information TechnologyJülichGermany
  3. 3.Peter Grünberg Institut 7 (PGI-7), Forschungszentrum Jülich GmbHJülichGermany
  4. 4.School of Computer Science and Engineering, Nanyang Technological UniversitySingaporeSingapore

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