The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.
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The authors declare that they have no conflicts of interest.
Dmitry Ivanovich Cheremisinov. Born 1947. Graduated from the Tomsk State University in radiophysics and radioelectronics in 1970. Received candidate’s degree in 1985. Currently is leading researcher at the United Institute of Informatics Problems of National Academy of Sciences of Belarus and Associate Professor at the Byelorussian State University of Informatics and Radioelectronics. Scientific interests: logic design and testing of discrete control systems, programming technologies, concurrent systems. Author of more than 200 publications including 3 monographs.
Liudmila Dmitrievna Cheremisinova. Born 1947. Graduated from the Tomsk State University in radiophysics and radioelectronics in 1971. Received candidate’s degree in Engineering Cybernetics and Information Theory in 1980 and Doctor of Sciences degree in System Analysis, Control and Information Processing in 2001. Currently is principal researcher at the United Institute of Informatics Problems of National Academy of Sciences of Belarus and Professor at the Byelorussian State University of Informatics and Radioelectronics. Scientific interests: discrete mathematics, logic design and testing of discrete control systems, concurrent systems. Author of more than 340 publications including 10 monographs.
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Cheremisinov, D., Cheremisinova, L. Subcircuit Pattern Recognition in Transistor Level Circuits. Pattern Recognit. Image Anal. 30, 160–169 (2020). https://doi.org/10.1134/S1054661820020042
- subcircuit extraction
- graph matching
- VLSI layout verification
- circuit reengineering