Abstract
We present a control-ready architecture for the self-testing of objects implemented with programmable logical matrices. The new architecture has a number of advantages over known ones. For this architecture, we solve the assignment problem that arises when test suites arrive from the test generator to the tested parts of the object. We present the self-testing procedure in a programmable matrix.
Similar content being viewed by others
References
Saleh, R., Wilton, S., Mirabbasi, S., Hu, A., et al., System-on-chip: Reuse and Integration, Proc. IEEE, 2006, vol. 94, no. 6, pp. 1050–1069.
Zorian, Y., Advances in Infrastructure IP, IEEE Design Test Comput., 2003, vol. 20, no. 3, pp. 49–57.
Quasem, M., Jiang, Z., and Gupta, S., Benefits of a SoC-specific Test Metodology, IEEE Design Test Comput., 2003, vol. 20, no. 3, pp. 68–77.
Menon, P., Xu, W., and Tessier, R., Design-specific Path Delay Testing in Lookup-table-based FPGAs, IEEE Trans. Comput. Aided Design Integr. Circuits Syst., 2006, vol. 25, no. 5, pp. 867–877.
Tahoori, M. and Mitra, S., Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2004, vol. 23, no. 2, pp. 261–272.
Tahoori, M. and Mitra, S., Application-independent Testing of FPGA Interconnects, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2005, vol. 24, no. 11, pp. 1774–1783.
Chakrabarty, K., Low-costModular Testing and Test Resource Partitioning for SoCs, IEE Proc. Comput. Digit. Tech., 2005, vol. 152, no. 3, pp. 427–441.
Lin, Y.-C., Lu, F., and Cheng, K.-T., Pseudofunctional Testing, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2006, vol. 25, no. 8, pp. 1535–1546.
Grecu, C., Ivanov, A., Saleh, R., and Pande, P., Testing Network-on-chip Communication Fabrics, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2007, vol. 26, no. 12, pp. 2201–2214.
Tehranipoor, M. and Rad, R., Built-in-self-test and Recovery Procedures for Molecular Electronics-based Nanofabrics, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2007, vol. 26, no. 5, pp. 943–957.
Cota, E., Kastensmidt, F., Cassel, M., Herve, M., et al., A High-fault-coverage Approach for the Test of Data, Control, and Handshake Interconnects in Mesh Network-on-chip, IEEE Trans. Comput., 2008, vol. 57, no. 9, pp. 1202–1214.
Li, L., Chakrabarty, K., Kajihara, S., and Swaminathan, S., Three-stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SoCs, IEE Proc. Comput. Digit. Techn., 2005, vol. 152, no. 6, pp. 704–712.
Das, S.R., Self-testing of Cores-based Embedded Systems with Built-in Hardware, IEE Proc. Circuits Devices Syst., 2005, vol. 152, no. 5, pp. 539–546.
Dutt, S., Verma, V., and Suthar, V., Built-in-self-test of FPGAs with Provable Diagnosabilities and High Diagnostic Coverage with Application to Online Testing, EEE Trans. Comput. Aided Design Integr. Circuits Syst., 2008, vol. 27, no. 2, pp. 309–326.
Aksenova, G.P. and Khalchev, V.F., Parallel-Sequential VLSI Self-Testing by Decomposition, Autom. Remote Control, 1991, no. 4, pp. 560–566.
Aksenova, G.P. and Khalchev, V.F., The Method of Parallel-sequential Built-in self-testing in Integrated Circuits of the Type FPGA, Autom. Remote Control, 2007, vol. 68, no. 1, pp. 149–159.
Zykov, A.A., Teoriya konechnykh grafov (Finite Graph Theory), Novosibirsk: Nauka, 1969.
Author information
Authors and Affiliations
Additional information
Original Russian Text © G.P. Aksenova, 2010, published in Avtomatika i Telemekhanika, 2010, No. 12, pp. 154–165.
Rights and permissions
About this article
Cite this article
Aksenova, G.P. Control-ready architecture for self-testing in programmable logical matrix structures. Autom Remote Control 71, 2633–2643 (2010). https://doi.org/10.1134/S000511791012012X
Received:
Published:
Issue Date:
DOI: https://doi.org/10.1134/S000511791012012X