Design and Implementation of Fractional Order Differintegrators Using Reduced s to z Transforms

  • K. RajasekharEmail author
  • B. T. KrishnaEmail author


The Design and implementation of fractional order digital differentiators and integrators is the main objective of this paper. Identify the novel reduced s to z transforms calculated using model order reduction techniques. Thus the transforms are discretized directly using Continued Fraction Expansion (CFE).The designed differentiators and integrators are implemented on Xilinx Spartan 3E field programmable gate arrays (FPGA) and are tested using the sinusoidal, square and triangular waveforms. The practical results agree with the theoretical ones.


discretization continued fraction expansion differentiators integrators FPGA 



Authors wish to acknowledge the university authorities, Jawaharlal Nehru Technological University Kakinada (JNTUK), Kakinada, Andhra Pradesh, India, for providing facilities to carry out this research.


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Copyright information

© Pleiades Publishing, Inc. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University KakinadaAndhra PradeshIndia

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