The charge collection from tracks of ionizing nuclear particles in CMOS trigger elements of the STG DICE type in the picosecond range is simulated using the 3D TCAD and the results are presented. The transient processes at the charge collection from tracks are analyzed (i) in the STG DICE D-trigger used for the cells of static memory, (ii) in the RS STG trigger, and (iii) in the logic C-element based on the STG DICE trigger for the asynchronous CMOS logic. The simulation results of the charge collection by the p–n junctions of both off and on transistors are presented. It is established that the charge collection from a track by MOS transistors begins in the off or on state and then transits to the charge collection in the inverse mode. The duration of the charge collection until the voltage extremum at the node of the trigger CMOS elements of the bulk 65-nm technology ranges from 5.5 to 17 ps, and the increments in the voltages of the extremums (maximums or minimums) at the nodes with respect to the voltages at the supply bus or at the common bus vary from 0.14 to 0.82 V. The duration of transistor occurrence in the inverse state ranges from 2 to 100 ps. The charge collection from tracks with the linear energy transfer (LET) of 60 MeV cm2/mg do not lead to the upset of the logical function of the elements for the tracks through the transistors of one group of the STG DICE trigger when there is sufficient spacing between the groups of transistors. The investigation results are oriented to designing systems which operate under the conditions of the action of single nuclear particles.
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Translated by E. Oborin
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Stenin, V.Y., Katunin, Y.V. Modeling the Charge Collection from a Track of an Ionizing Particle in Upset Hardened CMOS Trigger Elements. Russ Microelectron 48, 381–393 (2019) doi:10.1134/S1063739719060088
- logic element
- single nuclear particle
- noise immunity
- particle’s track