Russian Microelectronics

, Volume 48, Issue 3, pp 167–175 | Cite as

Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate

  • G. A. IvanovaEmail author
  • D. I. RyzhovaEmail author
  • S. V. Gavrilov
  • N. O. Vasilyev
  • A. L. Stempkovskii


The technological rules and design standards have become much more complicated with the increase in the degree of integration of microelectronic systems and the reduction of the technological dimensions of the basic elements to 32 nm and smaller. There are several thousand design restrictions for technologies with transistor sizes of 32 nm and smaller. Compliance with the full set of rules and design standards in the automatic mode becomes impossible when using the existing approaches to solving problems of logical and topological synthesis. This leads to the need for a large amount of manual work with the editing scheme and topology at the final stage of verification of the project as a whole. The transition to the use of regular structures in the lower layers of the topology has solved the problem of the increasing number of design standards for technologies of 22 nm and below. Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve level for advanced technologies with a vertical transistor gate have been proposed in this paper. The method of the inter-vent resynthesis of circuits taking into account the specific of designing circuits on Fin FET transistors is proposed. The proposed approach combines the methods of logical resynthesis and structural optimization of the circuit in order to achieve the required parameters (area, fault tolerance, or taking into account the design features of VLSI). An algorithm for combining the fragments of the topology of the standard cells and blocks that were obtained as a result of inter-valve resynthesis taking into account the specifics of designing circuits on FinFET transistors is proposed.



  1. 1.
    Gavrilov, S.V., Ivanova, G.A., and Manukyan, A.A., Design methods for custom complex functional units in the basis of elements with a regular topological structure in the polysilicon and diffusion layers, in Tr. VI Vserossiiskoi nauchno-tekhnicheskoi konferentsii “Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem – 2014” (Proceedings of the 6th All-Russia Conference on Development Problems of Promising Micro- and Nanoelectronic Systems–2014), Stempkovskii, A.L., Ed., Moscow: IPPM RAN, 2014, part 1, pp. 161–166.Google Scholar
  2. 2.
    Bryant, R.E., Graph-based algorithms for Boolean function manipulation, IEEE Trans. Comput., 1986, pp. 677–691.Google Scholar
  3. 3.
    Gavrilov, S.V., Gudkova, O.N., and Shchelokov, A.N., Logic timing nanometer circuits analysis using interval approach, Izv. YuFU, Tekh. Nauki, 2012, no. 7 (132), pp. 85–91.Google Scholar
  4. 4.
    Gavrilov, S.V., Metody analiza logicheskikh korrelyatsii dlya SAPR tsifrovykh KMOP SBIS (Methods of Analysis of Logical Correlations for CAD Digital CMOS VLSI), Moscow: Tekhnosfera, 2011.Google Scholar
  5. 5.
    Gavrilov, S.V., Glebov, A.L., and Stempkovskii, A.L., Metody logicheskogo i logiko-vremennogo analiza tsifrovykh KMOP SBIS (Methods of Logical and Logical-Temporal Analysis of Digital CMOS VLSI), Moscow: Nauka, 2007.Google Scholar
  6. 6.
    Gavrilov, S.V., Kareva, E.S., and Ryzhova, D.I., Algorithms of logical and physical synthesis of library elements with regular structure for design rules 32 nm, Izv. Vyssh. Uchebn. Zaved., Elektron., 2017, vol. 22, no. 4, pp. 369–378.Google Scholar
  7. 7.
    Wilkinson, B., Digital System Design, Englewood Cliffs: Prentice Hall, 1992.zbMATHGoogle Scholar
  8. 8.
    Gavrilov, S.V., Glebov, A.L., Pullela, S., Moore, S., Vijayan, G., Dharchoudhury, A., Rajendran, Panda, and Blaauw, D., Library-less synthesis for static CMOS combinational logic circuits, in Proceedings of the ICCAD-97, San Jose, CA, 1997, pp. 658–662.Google Scholar
  9. 9.
    Gavrilov, S.V. and Glebov, A.L., BDD-based circuit level structural optimization for digital CMOS, in Proceedings of the 1st International Workshop on Multi-Architecture Low Power Design, 1999, pp. 45–49.Google Scholar
  10. 10.
    Turgis, S., Azemad, N., and Auvergne, D., Design and selection of buffers for minimum power-delay product, in Proceedings of the European Design and Test Conference ED&TC-96, Paris, France, March 11–14, 1996, pp. 224–228.Google Scholar
  11. 11.
    Gavrilov, S.V., Kareva, E.S., Ryzhova, D.I., and Shchelokov, A.N., Physical model of regular structures based on FinFET transistors with independent gates, Izv. YuFU, Tekh. Nauki, 2017, no. 7 (192), pp. 175–185.Google Scholar
  12. 12.
    Gavrilov, S., Ryzhova, D., and Vasilyev, N., Models and methods of inter-gate resynthesis at the transistor level for nanoelectronic circuits based on FinFETs, in Proceedings of the 2018 IEEE Conference of Russian Young Researchers on Electrical and Electronic Engineering EIConRus, 2018, pp. 1364–1367.Google Scholar
  13. 13.
    Kushwah, R.S., Chauhan, M., Shrivastava, P., and Akashe, Sh., Modelling and simulation of finfet circuits with predictive technology models, Radioelectron. Commun. Syst., 2014, vol. 57, no. 12, pp. 553–558.CrossRefGoogle Scholar
  14. 14.
    Li, J., Behjat, L., and Schiffner, B., A structure based clustering algorithm with applications to vlsi physical design, in Proceedings of the 5th International Workshop on System-on-Chip for Real-Time Applications, July 20–24, 2005.
  15. 15.
    Manikandan, R., Effective clustering algorithms for VLSI circuit partitioning problems, Contemp. Eng. Sci., 2014, no. 7 (19), p. 923–929.

Copyright information

© Pleiades Publishing, Ltd. 2019

Authors and Affiliations

  1. 1.The Institute for Design Problems in Microelectronics, Russian Academy of SciencesMoscowRussia

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