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Russian Microelectronics

, Volume 48, Issue 3, pp 176–186 | Cite as

Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip

  • S. V. GavrilovEmail author
  • D. A. ZheleznikovEmail author
  • M. A. Zapletina
  • V. M. Khvatov
  • R. Zh. Chochaev
  • V. I. EnnsEmail author
Article
  • 9 Downloads

Abstract

A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose circuits produced at PJSC “Mikron”. The developed methodology includes new techniques to solve layout synthesis problems at different design flow stages, including the initial circuit decomposition, placement of logical elements, and the interconnections routing. Presented design flow makes it possible to accelerate the development of large IP blocks for reconfigurable systems-on-chip with multiple types of switching elements and system-on-chip components.

Notes

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Copyright information

© Pleiades Publishing, Ltd. 2019

Authors and Affiliations

  1. 1.Institute for Design Problems in Microelectronics, Russian Academy of SciencesZelenograd, MoscowRussia
  2. 2.Molecular Electronics Research Institute (JSC “NIIME”)Zelenograd, MoscowRussia

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