Russian Microelectronics

, Volume 48, Issue 3, pp 187–196 | Cite as

Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit

  • D. I. CheremisinovEmail author
  • L. D. Cheremisinova


In this paper, we address the problem of converting a flat CMOS circuit of transistors in the SPICE format into a hierarchical circuit of CMOS gates in the same format. This problem arises in the process of layout versus schematic (LVS) verification, as well as when reengineering integrated circuits. A method for recognizing subcircuits (CMOS gates) is described. The method is implemented as a C++ program; it recognizes subcircuits that are described by the same logic functions but are not isomorphic at the transistor level as different ones. This provides the isomorphism of the original and decompiled circuits.



  1. 1.
    Logic Gate Recognition in Guardian LVS—Silvaco. LogicGates.pdf. Accessed Jan. 4, 2018.Google Scholar
  2. 2.
    Hunt, V.D., Reengineering: Leveraging the Power of Integrated Product Development, New York: Wiley, 1993.Google Scholar
  3. 3.
    Baker, R.J., CMOS Circuit Design, Layout, and Simulation, 3rd ed., New York: Wiley-IEEE, 2010.CrossRefGoogle Scholar
  4. 4.
    Yang, L. and Shi, C.-J.R., FROSTY: a program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits, Integration, VLSI J., 2006, vol. 39, no. 4, pp. 311–339.CrossRefGoogle Scholar
  5. 5.
    Zhang, N., Wunsch, D.C., and Harary, F., The subcircuit extraction problem, in Proceedings of the IEEE International Behavioral Modeling and Simulation Workshop, 2005, vol. 33, no. 3, pp. 22–25.Google Scholar
  6. 6.
    Krasilnikova, L.V. and Pottosin, Yu.V., Partition of a transistor circuit into library modules from a given library, in Proceedings of the 2nd International Conference on Computer-Aided Design of Discrete Devices CAD DD’97, Minsk, Nov. 12–14, 1997, Minsk: Natl. Acad. Sci. Belarus Inst. Eng. Cybern., 1997, vol. 1, pp. 94–97.Google Scholar
  7. 7.
    Cheremisinov, D.I. and Cheremisinova, L.D., Search for frequently encountered subgraphs, in BIG DATA i analiz vysokogo urovnya, Sb. materialov IV Mezhdunar. nauch.-prakt. konf. (BIG DATA and Advanced Analytics, Proceedings of the Conference Minsk, Belarus’, May 3–4, 2018), Batura, M.P. et al., Eds., Minsk, 2018, pp. 171–176.Google Scholar
  8. 8.
    Netgen version 1.5 Tutorial. http://opencircuitdesign. com/netgen/tutorial/tutorial.html/. Accessed Feb. 16, 2018.Google Scholar
  9. 9.
    Harary, F., Graph Theory, Reading, MA: Addison-Wesley, 1969.CrossRefzbMATHGoogle Scholar
  10. 10.
    Rakitin, V.V., Integral’nye skhemy na komplementarnykh MOP-tranzistorakh: Uchebnoe posobie (Integrated Circuits on Complementary MOS Transistors, The School-Book), Moscow: MFTI, 2007.Google Scholar
  11. 11.
    Bushnell, M. and Agrawal V., Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI, New York: Springer Science, 2006.Google Scholar
  12. 12.
    Levitin, A.V., Algoritmy. Vvedenie v razrabotku i analiz (Algorithms. Introduction to the Development and Analysis), Moscow: Vil’yams, 2006.Google Scholar
  13. 13.
    Cheremisinova, L.D., Sintez i optimizatsiya kombinatsionnykh struktur SBIS (Synthesis and Optimization of Combining Structures of VLSI), Minsk: OIPI NAN Belarusi, 2005.Google Scholar
  14. 14.
    Belous, A.I., Emel’yanov, V.A., and Turtsevich, A.S., Osnovy skhemotekhniki mikroelektronnykh ustroistv (Fundamentals of Circuit Design of Microelectronic Devices), Moscow: Tekhnosfera, 2012.Google Scholar
  15. 15.
    Zakrevskii, A.D., Pottosin, Yu.V., and Cheremisinova, L.D., Logicheskie osnovy proektirovaniya diskretnykh ustroistv (The Logical Principles of the Design of Discrete Devices), Moscow: Fizmatlit, 2007.Google Scholar
  16. 16.
    Junttila, T. and Kaski, P., Engineering an efficient canonical labeling tool for large and sparse graphs, in Proceedings of the 9th Workshop on Algorithm Engineering and Experiments ALENEX, 2007, pp. 135–149.Google Scholar
  17. 17.
    Rabaey, J.M., Chandrakasan, A., and Borivoje, N., Digital Integrated Circuits, Upper Saddle River, NJ: Pearson, 2003.Google Scholar

Copyright information

© Pleiades Publishing, Ltd. 2019

Authors and Affiliations

  1. 1.United Institute of Informatics Problems, National Academy of Sciences of BelarusMinskBelarus

Personalised recommendations