Automation and Remote Control

, Volume 65, Issue 11, pp 1847–1859 | Cite as

Functional Tests for RISC-microprocessors

  • S. G. Sharshunov


The well-known models and concepts of functional testing of microprocessors are described. The properties of the RISC-architecture that aid in applying effective approaches to hardware testing are stated. Functional decomposition is used to develop a sequence of actions implemented in designing tests. Special attention is paid to testing of control units. The RISC-architecture has shown to be helpful in designing effective algorithms for testing at the architectural level. The designed procedures detect most of the defects in control circuits indirectly through data processing and storing devices without the use of control units.


Mechanical Engineer System Theory Control Unit Functional Test Control Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Stolichny, C., Davies, R., McKernan, P., and Truong, T., Manufacturing Test Development and Coverage Analysis, IEEE Design Test Comput., 1998, vol. 15, no. 3, p. 1.Google Scholar
  2. 2.
    Reilly, M., Designing an Alpha Microprocessor, IEE Comput., July 1999, pp. 25–34.Google Scholar
  3. 3.
    Robach, C. and Saucier, G., Dynamic Testing of Control Units, IEEE Trans. Comput., 1978, C-27(7), pp. 617–623.Google Scholar
  4. 4.
    Thatte, S.M. and Abraham, J.A., A Methodology for Functional Level Testing of Microprocessors, Proc. 8th Int. Symp. Fault Tolerant Comput., Touluse, France, 1978, pp. 90–95.Google Scholar
  5. 5.
    Thatte, S.M. and Abraham, J.A., Test Generation for Microprocessors, IEEE Trans. Comput., 1980, C-29(6), pp. 429–441.Google Scholar
  6. 6.
    Brahme, D. and Abraham, J.A., Functional Testing of Microprocessors, IEEE Trans. Comput., 1984, C-33(6), pp. 475–485.Google Scholar
  7. 7.
    Shen, L. and Su, S.Y.H., A Functional Testing Method for Microprocessors, IEEE Trans. Comput., 1988, C-37(10), pp. 1288–1293.Google Scholar
  8. 8.
    Sharshunov, S.G., Designing Tests for Microprocessor. A General Model. Testing of Data Processing, Avtom. Telemekh., 1985, no. 1, pp. 145–55.Google Scholar
  9. 9.
    Sharshunov, S.G. and Tchipulis, V.P., On Generating Tests for Microprocessors, Measurement, 1986, vol. 4,no. 1, pp. 28–38.Google Scholar
  10. 10.
    Tchipulis, V.P. and Sharshunov, S.G., Analiz i postroenie testov tsifrovykh programmno-upravlyaemykhustroistv(Analysis and Design of Tests for Digital Program-Controlled Devices), Moscow: Energoat-omizdat, 1992.Google Scholar
  11. 11.
    Van de Goor, A.J. and Verhallen, Th.J.W., Functional Testing of Current Microprocessors (Applied to the Intel i860 TM ), Proc. IEEE Int. Test Conf., 1992, pp. 684–695.Google Scholar
  12. 12.
    Koshevenko, A.V. and Sharshunov, S.G., Functional Testing of RISC-Microprocessors, Avtom. Tele-mekh., 1998, no. 10, pp. 147–158.Google Scholar
  13. 13.
    Suk, D.S. and Reddy, S.M., A March Test for Functional Faults in Semiconductor Random Access Memories, IEEE Trans. Comput., 1981, C-29(6), pp. 982–985.Google Scholar
  14. 14.
    Glushkov, V.M., Theory of Automata and Formal Transformations of Microprograms, Kibernetika, 1965, no. 5, pp. 1–9.Google Scholar
  15. 15.
    Polyakov, V., Microprocessor: Between the Past and Future, Komp'yuter-Press, 1996, no. 4, pp. 62–67.Google Scholar
  16. 16.
    Katevenis, M.G.H., Sekuin, K.H., Patterson, D.A., and Shernburn, R.U., RISC: Effective Architectures for VLSI Computers, in Elektronika SBIS. Proektirovanie mikrostruktur (VLSI Electronics. Design ofMicrostructures), Moscow: Mir, 1989.Google Scholar
  17. 17.
    Kautz, W.H., Testing for Faults in Cellular Logic Arrays, Proc. 8th Ann. Symp. Switching, Automata Theory, 1967, pp. 161–174.Google Scholar
  18. 18.
    Turcat, C. and Verdillon, A., Recursion and Testing of Combinational Circuits, IEEE Trans. Comput., 1976, C-25(6), pp. 625–654.Google Scholar
  19. 19.
    McLellan, E., The Alpha AXP Architecture and 21064 Processor, IEEE Micro, 1993, pp. 36–47.Google Scholar
  20. 20.
    Rybakov, A., PowerPC Processors, Komp'yuter-Press, 1996, no. 2, pp. 86–93.Google Scholar
  21. 21.
    Ultra Sparc TM Programmer Reference Manual. SPARC Technology Business, 1995, Sept. 18.Google Scholar
  22. 22.
    Shen, J.P. and Schuette, On-Line Self-Monitoring using Signatured Instruction Streams, Proc. Int. Test Conf., Philadelphia, 1983, pp. 275–282.Google Scholar
  23. 23.
    Novikov, A.S., Metody i algoritmy testirovaniya pamyati EVM s obnaruzhemiem kratnykh funkt-sianal'nykh neispravnostei (Methods and Algorithms for Testing Computer Memory with Detection of Multiple Functional Faults), Doctoral Dissertation, Vladivostok, 2002.Google Scholar
  24. 24.
    Kuznetsov, O.Yu., Funktsional'noe testirovanie upravlyayushchego oborudovaniya RISC-mikroprotses-sorov, primenitel'no k arkhitekture SPARC-V9 (Functional Testing for Control Units of RISC-Micro-processors under SPARC V9 Architecture), Doctoral Dissertation, Vladivostok, 2002.Google Scholar

Copyright information

© MAIK “Nauka/Interperiodica” 2004

Authors and Affiliations

  • S. G. Sharshunov
    • 1
  1. 1.Far Eastern State Academy of Economics and ManagementVladivostokRussia

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