Skip to main content
Log in

Easily Testable Realization of a Circuit on the Basis of Polynomial Representation of Output Functions

  • Published:
Automation and Remote Control Aims and scope Submit manuscript

Abstract

Realization of combinational circuits on the basis of the expansion of output functions in the class of polynomials is suggested. It is shown that a universal test sequence from the n + 1 set enables detecting all single faults in the circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

REFERENCES

  1. Goryashko, A.P., Sintez diagnostiruemykh skhem vychislitel'nykh ustroistv (Synthesis of Diagnosable Circuits of Computational Devices), Moscow: Nauka, 1987.

    Google Scholar 

  2. Reddy, S.M., Easily Testable Realization for Logic Functions, IEEE Trans. Comput., 1971, vol. C-21, pp. 1183-1188.

    Google Scholar 

  3. Hayes, J., On Realization of Boolean Functions Requiring a Minimal or Near Minimal Number of Tests, Proc. IEEE Test. Conf., 1971, no. 6, pp. 1506-1513.

  4. Debnath, D. and Sasao, T., GRMIN: A Heuristic Simplification Algorithm for Generalized Reed-Muller Expressions, IEEE Proc. Comput. Digital Technol., 1996, vol. 143, no. 6, pp. 376-384.

    Google Scholar 

  5. Yamada, T., Easily Testable AND-EXOR Combinational Logic Circuits, IEEE Trans., 1983, vol. J. 66-D, no. 1, pp. 105-110.

    Google Scholar 

  6. Sasao, T. and Fujiwara, H., A Design Method of AND-EXOR PLA's with Universal Test Sets, Tech. Report IECE J. FTS 86-25, 1987.

  7. Sarabi, A. and Perkowski, M.A., Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed Polarity AND/XOR Canonical Networks, Proc. Design Autom. Conf., 1992, pp. 20-35.

  8. Perkowski, M.A., Csanky, L., Sarabi, A., et al., Fast Minimization of Mixed-Polarity AND-XOR Canonical Networks, Proc. ICCD-92, 1992, pp. 33-36.

  9. Sasao, T., Easily Testable Realization for Generalized Reed-Muller Expressions, IEEE Trans. Comput., 1997, vol. 46, pp. 709-716.

    Google Scholar 

  10. Latypov, R., Self-Testable Circuits with Single Fault Detection, Proc. Reed-Muller Workshop, Chiba, Japan, 1995, pp. 203-205.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Latypov, R.K. Easily Testable Realization of a Circuit on the Basis of Polynomial Representation of Output Functions. Automation and Remote Control 62, 2015–2019 (2001). https://doi.org/10.1023/A:1013724528462

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1013724528462

Keywords

Navigation