An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment


Post-silicon validation is a major challenge due to finite controllability and observability of actual silicon and makes debug a complex task. The trace signals routed from CPUs and other sources are translated by sampling unit to time-stamped trace messages and stored in trace buffer. Time stamp generated is not the exact time at which event has occurred. Hence, trace data read from trace buffer in post-silicon environment is not accurate from debug perspective. This is corrected by finding the variable delay along with various paths observed between two viewpoints, one being the source at which the event occurs and the other being the destination where the event gets recorded. One method to achieve time accurate debug data is by correlating the time at which data transaction event occurs at the signal with the time at which the trace data for that particular transaction event gets time-stamped. The major advantage is the successful reconstruction of pre-silicon environment for that particular post-silicon environment and enabling data to be viewed on the fly.


Validation is proven to be the major bottleneck in SOC design, and the study suggests that 70% of the overall time and effort is spent on SOC verification and validation  [1]. The process of verifying the correctness and adequacy of the design before sending for fabrication is referred to as pre-silicon validation. On the other hand, post-silicon validation ensures the correct functionality of manufactured chip under different operating conditions before sending for mass production. In the recent times, the design has been provided with post-silicon validation and debug infrastructure [2]. The observability limitation of silicon debug is overcome by an efficient trace buffer technique.

When an unintended system behavior is observed, the root cause of the issue is unknown. This can be resolved by non-intrusive debugging with trace of analyzing the trace data taken around that point in time when the issue occurs. The debugging with trace enables to get a log of program execution with time information added. The main advantage of this type of debugging is that it does not impact the code execution and timing behavior. Tracing helps in finding the causes of system’s misbehavior and analyzing performance. Trace data can contain both program and data information, enabling the debug of possible mistakes in software easier.

Fig. 1

Flow of trace buffer-based post-silicon debug

The flow of trace buffer-based post-silicon debug is depicted in Fig. 1. Debugging of specific features can be done via trigger lines that collect debug events from various sources like CPUs, interrupt requesters, and peripherals. The Central Suspend Switch allows to configure which CPUs or peripherals to be halted as a reaction to a debug event. The test case is flashed on the silicon, and trace IP configurations are performed. Tracing of all transaction activities performed by particular trace source or peripheral is started. The transaction activities occurring at the signal level of trace IP are converted into time-stamped trace data. These trace data are pushed into trace buffer  [3]. Once trace buffer is filled, tracing stops and the content of trace buffer is read by trace viewer. Trace viewer displays all the activities of the trace source captured in trace buffer.

Proposed Methodology

The block diagram of trace IP is shown in Fig. 2. The trace source performing any transaction activity like read operation, write operation, etc., can be captured using trace IP for debugging. This transaction activity is recorded at trace IP signals at time \({{T}}_{\mathrm{Signal}}\). Each trace source has an observation block. Each observation block has trace units which sample the signal-level information into time-stamped trace messages. Trace units contain a sampling unit to generate different time-stamped trace messages at the same time. Data buffers are present in trace units to store the time-stamped trace messages.

Fig. 2

Block diagram of trace IP

Embedded cross connect is used to synchronize trace message streams from different observation blocks with their appropriate time stamps and send to trace host. The time information is provided in accordance with the trace clock. All the trace messages cannot be transported from the target to the host at the very instant of their creation. Trace memory controller has a memory-efficient message aligner to sort the time-stamped trace messages from different trace sources into the trace buffer.

All the trace messages get their time stamp at the generation point of time, i.e., the time when the trace messages are put in data buffers. But, the time stamp is not the exact time at which the transaction event has occurred. The trace data captured at time \({T}_{\mathrm{Trace}}\) in the trace viewer read from trace buffer are not accurate from the debug perspective. There is a variable delay observed when captured on the trace viewer.

Correlation of Transaction Timing

The problem of inaccurate trace data can be overcome by correlating the timing of transaction activity between the pre-silicon and post-silicon environment. When trace IP is used for tracing the event of any trace source, trace data are read from trace buffer both in the pre-silicon and in the post-silicon environment. The time-stamped trace data are captured at time \({T}_{\mathrm{Trace}}\) in trace viewer. But, the same event would have occurred at time \({T}_{\mathrm{Signal}}\) at trace IP signals in pre-silicon environment.

Fig. 3

Overview of the proposed methodology

For each trace source (CPUs, Bus, and other peripherals), hardware and software trace data are obtained. Hardware trace data correspond to the transaction activity performed on the bus and other peripherals. Software trace data correspond to software hooks added in test patterns to understand the timing and functionality of event performed by trace source. The trace data were captured on trace viewer via an interface. Time accurate debug data are achieved by correlating the time at which data transaction event occurs at the signal with the time at which trace data for that particular transaction event get time-stamped as illustrated in Fig. 3.

Fig. 4

Flow diagram of the proposed methodology

The test case is run in both the post-silicon and pre-silicon environment, and the corresponding trace and waves are obtained. Raw trace data are converted into encoded trace data and stored in trace buffer. Every time trace data are read from trace buffer, trace viewer decodes, and displays. Trace viewer file and signal-captured file are converted to VCD file (value change dump). These VCD files are converted to the corresponding FSDB files (fast signal database). These FSDB files are merged and converted to VCD file. Finally, a mathematical formula is obtained for the variable delay along with various observation blocks of different trace sources as illustrated in Fig. 4.

Fig. 5

Variable delay

The variable delay \(\delta _{ijkl}\) can be mathematically expressed as

$$\begin{aligned} \delta _{ijkl} = \delta _{\mathrm{constant}} + \delta _{\mathrm{variable}} \end{aligned}$$

where \(\delta _{ijkl}\) = variable delay along with various observation blocks for different trace sources, i = type of observation block, j = type of functionality either program trace or data trace, k = type of transaction activity either read or write operation, l = types of message or destination, \(\delta _{\mathrm{constant}}\) = minimum delay under ideal conditions, \(\delta _{\mathrm{variable}}\) = maximum delay due to aggressor activity on victim (Fig. 5).

The variable delay \(\delta _{ijkl}\) depends on these four parameters explained above. It also depends on the priority of transaction activity, time required to complete the execution and bus traffic. \(\delta _{\mathrm{constant}}\) is the minimum delay obtained under any ideal condition. \(\delta _{\mathrm{variable}}\) is the maximum delay obtained under the worst condition influenced by the aggressor activity on victim.


Figure 6 illustrates the transaction activities recorded in trace and wave VCD files. \(\delta _{1}\) and \(\delta _{2}\) are the delays observed between the event occurred on trace IP signals and event captured on trace viewer.

Fig. 6

Transaction event observed in both pre and post-silicon environment

Figure 7 shows how these variable delays can be obtained from the pre-silicon environment. Using this delay, post-silicon debug trace data are made more timing accurate.

Fig. 7

Transaction event occurred in pre-silicon environment

Conclusion and Future Work

The proposed methodology proves to be an efficient method to improve the time accuracy of post-silicon debug trace data. It also proves to establish a mathematical correlation of timing of transaction event between the pre-silicon and post-silicon environment, enabling the data to be viewed on the fly in real time. The missing attributes in the post-silicon environment can be resolved by mathematically correlating with the pre-silicon environment. The proposed methodology is clear only about minimum delay, and the \(\delta _{\mathrm{variable}}\) has to be addressed in the future. The variable delay depends on the priority of transaction activity, time hold, influence of local bus, global bus, and memories. The probability of variable delay value change depends on whether the event is influenced by one entity or many. Using machine learning, variable delay can be obtained for various aggressor activities influencing the victim.


  1. 1.

    Mishra P, Morad R, Ziv A, Ray S. Post-silicon validation in the soc era: a tutorial introduction. IEEE Des. Test. 2017;34(3):6892.

    Article  Google Scholar 

  2. 2.

    Basu K, Mishra P. Efficient trace data compression using statically selected dictionary. In: 2011 IEEE 29th VLSI test symposium (VTS) (IEEE); 2011. p. 1419

  3. 3.

    Basu Kanad. Structural signal selection for post-silicon validation. Post-silicon validation and debug. Cham: Springer; 2019. p. 33–56.

    Google Scholar 

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This article is part of the topical collection “Advances in Computational Intelligence, Paradigms and Applications” guest edited by Young Lee and S. Meenakshi Sundaram.

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Anala, Gayathri, S., Ramaswamy, R. et al. An Approach to Mathematically Correlate Timing of Transaction Activity Between Pre-silicon and Post-silicon Environment. SN COMPUT. SCI. 1, 125 (2020).

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  • Debug
  • Correlation
  • Observability
  • Controllability
  • Trace