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Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

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Abstract

Based on 3D-TCAD simulations, single-event transient (SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator (FDSOI) transistors are investigated. This work presents a comparison between 28-nm technology and 0.2-μm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

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Authors and Affiliations

  1. College of Computer, National University of Defense Technology, Changsha, 410073, China

    Jing-Yan Xu, Shu-Ming Chen, Rui-Qiang Song, Zhen-Yu Wu & Jian-Jun Chen

  2. National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, 410073, China

    Shu-Ming Chen

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  1. Jing-Yan Xu
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  2. Shu-Ming Chen
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  4. Zhen-Yu Wu
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  5. Jian-Jun Chen
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Correspondence to Jing-Yan Xu or Shu-Ming Chen.

Additional information

This work was supported by the National Natural Science Foundation of China (Nos. 61434007 and 61376109).

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Xu, JY., Chen, SM., Song, RQ. et al. Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs. NUCL SCI TECH 29, 49 (2018). https://doi.org/10.1007/s41365-018-0391-3

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  • DOI: https://doi.org/10.1007/s41365-018-0391-3

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