Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

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Abstract

Based on 3D-TCAD simulations, single-event transient (SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator (FDSOI) transistors are investigated. This work presents a comparison between 28-nm technology and 0.2-μm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

Keywords

Single-event transient Charge collection Bipolar amplification Fully depleted silicon-on-insulator 

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Copyright information

© Shanghai Institute of Applied Physics, Chinese Academy of Sciences, Chinese Nuclear Society, Science Press China and Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.College of ComputerNational University of Defense TechnologyChangshaChina
  2. 2.National Laboratory for Parallel and Distributed ProcessingNational University of Defense TechnologyChangshaChina

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