Mapping complex hierarchical reconfigurable tasks on distributed architectures are classically an NP-hard problem. The current paper introduces a new software specification of these tasks with two-dimensional hierarchy levels DAGs. Each DAG is composed of multi-hierarchical subDAGs to specify graphs of complex software task graphs. We also propose a heuristic algorithm for mapping the new reconfigurable hierarchical model on multi-core MP-SOC architectures. In the proposed software model, an application is seen as a DAG of tasks each of which is considered as a subDAG composed of elementary functions. The proposed algorithm acts in three steps: First, we map the subDAGs at the deepest level of hierarchy into processing units (cluster of processors). Then we map each task on a particular processor. Finally we map elementary functions on processor cores. Experimental results of the proposed algorithms show an increase of performance in terms of execution time and energy consumption. Our algorithm is also efficient in terms of communication cost approved by simulation results applied to large number of tasks.
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Ghribi, I., Ben Abdallah, R., Khalgui, M. et al. On Mapping of Reconfigurable Hierarchical Tasks to MP-SoC-Oriented Architectures Under Real-Time and Energy Constraints. Iran J Sci Technol Trans Electr Eng 45, 207–220 (2021). https://doi.org/10.1007/s40998-020-00343-3
- Embedded system
- Hierarchical real-time task
- MP-SOC platform
- Energy constraint