Applications such as image, audio, and video processing are tolerant to certain amounts of error. This tolerance/resiliency can be exploited to construct approximate circuits with improved design parameters such as area, power, and delay. This paper presents a high-speed yet energy-efficient approximate multiplier for low-power applications. In the proposed scheme, the operands are divided into accurate (significant) and rounded (insignificant) sections at half of the operand bit-length. Further, simplified multiplication operations are performed between these sections to obtain the final product. The proposed multiplier architecture involves an accurate small width multiplier as well as shifter blocks, which leads to delay- and energy-efficient architecture. The performance of proposed multiplier over the existing is evaluated by coding the designs in Verilog implementing on Artix7 family XC7A100TCSG324 FPGA device using Xilinx ISE tool chain. The simulation results show 23–31% and up to 26% in delay and energy savings, respectively, over the existing approximate architectures.
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Alioto M (2012) Ultra-low power vlsi circuit design demystified and explained: a tutorial. IEEE Trans Circuits Syst I: Regular Papers 59(1):3–29
Gupta V, Mohapatra D, Raghunathan A, Roy K (2012) Low-power digital signal processing using approximate adders. IEEE Trans Computer-Aided Design Integr Circuits Syst 32(1):124–137
Mahdiani HR, Ahmadi A, Fakhraie SM, Lucas C (2009) Bio-inspired imprecise computational blocks for efficient vlsi implementation of soft-computing applications. IEEE Trans Circuits Syst I: Regular Papers 57(4):850–862
Venkatesan R, Agarwal A, Roy K, Raghunathan A (2011) Macaco: modeling and analysis of circuits for approximate computing. In: 2011 IEEE/ACM international conference on computer-aided design (ICCAD). IEEE, pp 667–673
Narayanamoorthy S, Moghaddam HA, Liu Z, Park T, Kim NS (2014) Energy-efficientapproximate multiplication for digital signal processing andclassification applications. IEEE Trans Verylarge Scale Integr (VLSI) Syst 23(6):1180–1184
Ansari MS, Cockburn BF, Han J (2019) A hardware-efficient logarithmic multiplier with improved accuracy. In: 2019 design, automation & test in europe conference & exhibition (DATE). IEEE, pp 928–931
Lu S-L (2004) Speeding up processing with approximation circuits. Computer 37(3):67–73
Zhu N, Goh WL, Wang G, Yeo K S (2010) Enhanced low-power high-speed adder for error-tolerant application. In: 2010 international soc design conference. IEEE, pp 323–327
Zhu N, Goh WL, Zhang W, Yeo KS, Kong ZH (2009) Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(8):1225–1229
Patel S, Garg B, Mahajan A, Rai S (2019) Area-delay efficient and low-power carry skip adder for high performance computing systems. In: IEEE international symposium on smart electronic systems (iSES) (Formerly iNiS). IEEE, pp 295–298
Garg B, Bisht Y (2019) A novel high performance reverse carry propagate adder for energy efficient multimedia applications. In IEEE international symposium on smart electronic systems (iSES) (Formerly iNiS). IEEE, pp 291–294
Garg B, Patel SK (2021) Reconfigurable carry look-ahead adder trading accuracy for energy efficiency. J Sign Process Syst 93:99–111. https://doi.org/10.1007/s11265-020-01542-1
Kulkarni P, Gupta P, Ercegovac M, (2011) Trading accuracy for power with an underdesigned multiplier architecture. In: 2011 24th internatioal conference on VLSI design. IEEE, pp 346–351
Garg B, Sharma G (2017) Acm: An energy-efficient accuracy configurable multiplier for error-resilient applications. J Elect Testing 33(4):479–489
Hashemi S, Bahar R, Reda S, (2015) Drum: a dynamic range unbiased multiplier for approximate applications. In: Proceedings of the IEEE/ACM international conference on computer-aided design. IEEE Press, pp 418–425
Zendegani R, Kamal M, Bahadori M, Afzali-Kusha A, Pedram M (2016) Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(2):393–401
Ebrahimi Z, Ullah S, Kumar A (2020) Leap: leading-one detection-based softcore approximate multipliers with tunable accuracy. In: 2020 25th Asia and South Pacific design automation conference (ASP-DAC). IEEE, pp. 605–610
Ansari MS, Mrazek V, Cockburn BF, Sekanina L, Vasicek Z, Han J (2020) Improving the accuracy and hardware efficiency of neural networks using approximate multipliers. IEEE Trans Very Large Scale Integ VLSI) Syst 28(2):317–328. https://doi.org/10.1109/TVLSI.2019.2940943
Garg B, Patel SK, Dutt S (2020) LoBA: a leading one bit based imprecise multiplier for efficient image processing. J Electron Test 36:429–437. https://doi.org/10.1007/s10836-020-05883-4
Garg B, Goteti V C, Sharma G (2016) A low-cost energy efficient image scaling processor for multimedia applications. In: VLSI Design and Test (VDAT), 2016 20th international symposium on. IEEE, pp 1–6
Garg B, Sharma G (2016) A quality-aware energy-scalable gaussian smoothing filter for image processing applications. Microprocess Microsyst 45:1–9
Harley RM et al (2009) The pocket handbook of image processing algorithms in C. Prentice-Hall, New Jersey
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Satti, P., Agrawal, P. & Garg, B. LORAx: A High-speed Energy-efficient Lower-Order Rounding-based Approximate Multiplier. Natl. Acad. Sci. Lett. (2021). https://doi.org/10.1007/s40009-020-01036-5
- Arithmetic design
- Approximate architecture
- Energy-efficient design
- Image processing