, Volume 8, Issue 1, pp 264–271 | Cite as

Power and Noise Optimization Techniques of RF Active Inductor Using Multi-Finger Gate Transistors

  • Mongia Mhiri
  • Aymen Ben Hammadi
  • Fayrouz Haddad
  • Sehmi Saad
  • Kamel Besbes


In this paper, an optimization technique for active inductor circuit forward noise, size area, and power dissipation is proposed through careful selection of the number of gate fingers N f of a nanoscale MOS transistor. According to simulation results, the application of supply voltage scaling and multi-gate finger transistor techniques can therefore introduce simultaneously a reduction in power consumption around 60% (from 3.35 to 1.32 mW) and a minimization in noise performance at 2 GHz from 3.15 to 2.1 ɳV/√Hz with a small size area and wide tuning range.


Active inductor Multi-finger gate Noise optimization Supply voltage scaling Low power 



This work was supported by the Microelectronics and instrumentation Laboratory (University of Monastir, Tunisia) in collaboration with the Institute of Materials, Microelectronics and Nanosciences in Provence (Aix-Marseille University, France).


  1. 1.
    Bult, K. (2006). The effect of technology scaling on power dissipation in analog circuits. In: Analog circuit design (pp. 251–294). Springer Netherlands.Google Scholar
  2. 2.
    Huang, S., Diao, S., and Lin, F. (2017). A 0.7-V, 8.9μA compact temperature-compensated CMOS subthreshold voltage reference with high reliability, Analog Integrated Circuits and Signal Processing, (1–9).Google Scholar
  3. 3.
    Nguyen, T. K., Kim, C. H., Ihm, G. J., Yang, M. S., & Lee, S. G. (2004). CMOS low-noise amplifier design optimization techniques. IEEE Transactions on Microwave Theory and Techniques, 52(5), 1433–1442.CrossRefGoogle Scholar
  4. 4.
    Vertregt, M., & Scholtens, P. (2004). Assessment of the merits of CMOS technology scaling for analog circuit design. Proc ESSCIRC, 57–63.Google Scholar
  5. 5.
    Kang, M., & Yun, I. (2011). Modeling electrical characteristics for multi-finger MOSFETs based on drain voltage variation. Transactions on Electrical and Electronic Materials, 12(6), 245–248.MathSciNetCrossRefGoogle Scholar
  6. 6.
    Apratim, R., & Shahriar Rashid, S. M. (2013). A power-efficient process selection, gain optimization, and noise canceling technique for a 130-nm microwave amplifier. Journal of Electrical System, 1(100), 113.Google Scholar
  7. 7.
    Jeon, J., & Kang, M. (2016). Circuit level layout optimization of MOS transistor for RF and noise performance improvements. IEEE Transactions on Electron Devices, 63(12), 4674–4677.CrossRefGoogle Scholar
  8. 8.
    El-Kenawy, K., & Dessouky, M. (2016). Stress-aware analog layout devices pattern generation. In IEEE 11th International Symposium on Design & Test (IDT) (pp. 233-238).Google Scholar
  9. 9.
    Ahish, S., Sharma, D., Kumar, Y. B. N., & Vasantha, M. H. (2016). DC and analogue/radio frequency performance optimisation of heterojunction double-gate tunnel field-effect transistor. Micro & Nano Letters, 11(8), 407–411.CrossRefGoogle Scholar
  10. 10.
    Momen, H. G., Yazgi, M., Kopru, R., & Saatlo, A. N. (2017). Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters. Integration, the VLSI Journal, 58, 22–26.CrossRefGoogle Scholar
  11. 11.
    Jin, X., Ou, J.-J., Chen, C.-H., Liu, W., Deen, M. J., Gray, P. R. and Hu, C.. (1998). An effective gate resistance model for CMOS RF and noise modeling. International Electron Devices Meeting Technical Digest, 961-964.Google Scholar
  12. 12.
    Fukui, H. (1979). Optimal noise figure of microwave GaAs MESFET’s. IEEE Transactions on Electron Devices, 26(7), 1032–1037.CrossRefGoogle Scholar
  13. 13.
    Tang, X. (2012). Apport des lignes à ondes lentes S-CPW aux performances d’un front-end millimétrique en technologie CMOS avancée. Thesis. Grenoble Alpes University.Google Scholar
  14. 14.
    Chen, C., Srivastava, A., & Sarrafzadeh, M. (2001). On gate level power optimization using dual-supply voltages. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9, 616–629.CrossRefGoogle Scholar
  15. 15.
    Yeh, C., & Chang, M. (1999). Gate-level voltage scaling for low-power design using multiple supply voltages. IEE Proceedings, Circuits, Devices and Systems, 146, 334–339.CrossRefGoogle Scholar
  16. 16.
    Hammadi, A. B., Mhiri, M., Haddad, F., Saad, S., & Besbes, K. (2017). An enhanced design of multi-band RF band pass filter based on tunable high-Q active inductor for nano-satellite applications. Journal of Circuits, Systems and Computers, 26(4), 1750055.CrossRefGoogle Scholar
  17. 17.
    Hammadi, A. B., Mhiri, M., Haddad, F., Saad, S., & Besbes, K. (2014). High-Q RF CMOS tunable active inductor for multistandard applications. International Review on Modelling and Simulations (IREMOS), 7(4), 567–574.CrossRefGoogle Scholar
  18. 18.
    RAFEI, M., & Mosavi, M. R. (2012). Cancellation of series-loss resistance in UWB active inductors using RC feedback. Iranian Journal of Electrical & Electronic Engineering, 8(2), 129–137.Google Scholar
  19. 19.
    Li, C., Gong, F., & Wang, P. (2010). Analysis and design of a high-Q differential active inductor with wide tuning range. IET circuits, devices & systems, 4(6), 486–495.CrossRefGoogle Scholar
  20. 20.
    Momen, H. G., Yazgi, M., Kopru, R., & Saatlo, A. N. (2016). Design of a new low loss fully CMOS tunable floating active inductor. Analog Integrated Circuits and Signal Processing, 89(3), 727–737.CrossRefGoogle Scholar
  21. 21.
    Koo, J., Lee, S., & Jeonga, Y. (2016). CMOS 2-port active inductor using LC resonance circuit. IDEC Journal of Integrated Circuits and Systems, 3(1), 7–12.Google Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2017

Authors and Affiliations

  1. 1.Microelectronics and Instrumentation LaboratoryUniversity of MonastirMonastirTunisia
  2. 2.Aix-Marseille UniversityMarseilleFrance
  3. 3.Center for Research in Microelectronics and NanotechnologySousseTunisia

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