A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Silicon (2021)Cite this article

Abstract

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (ION/IOFF) = ~107 and good ON-OFF performance metric Q = gm/SS = 2.06 × 10−5 S-dec/μm-mV even at 5 nm LG. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of gm by ~10% have been noticed from SiO2 + HfO2 to Si3N4 + HfO2. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like ft, τ, and GBW. The Air single-k spacer shows good performance for RF applications with ft = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at LG = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO2, Si3N4) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications.

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Acknowledgements

The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.

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  1. Department of Electronics & Communication Engineering, National Institute of Technology Warangal, Warangal - 506004, Hanamkonda, India

    V. Bharath Sreenivasulu & Vadthiya Narendar

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  1. V. Bharath Sreenivasulu
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Contributions

V. Bharath Sreenivasulu: Writing- Original draft preparation, Formal Analysis, Investigation, Simulation, Data Curation.

V. Narendar: Conceptualization, Methodology, Supervision.

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Correspondence to V. Bharath Sreenivasulu.

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Sreenivasulu, V.B., Narendar, V. A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length. Silicon (2021). https://doi.org/10.1007/s12633-021-00987-8

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Keywords

  • Tri-gate (TG) JL SOI FinFET
  • High-k metal gate
  • Single-k/dual-k spacer
  • Analog/RF and linearity parameters
  • Dynamic power
  • Power consumption