A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications

Abstract

A 2-dimensional electrostatic potential modeling of fully depleted channel, with high-k based dual work function double gate (DWFDG) MOSFET, has been developed in this paper. The expression for electrostatic potential of DMDG has been developed using 2-D Poisson’s equation with appropriate device boundary conditions along the device gate length. The high-k based DWFDG MOSFET shows a significant decrease in short channel effects (SCEs), by using step in electrostatic potential near the interface of gate materials (M1) and (M2). The impact of device limitations such as electrostatic potential with oxide thickness, channel thickness, different gate bias and drain bias on the capability of the device has been examined using novel analytical model. The validation of the analytical modeling results are verified with numerical simulation by using 2-dimentional Sentaurus TCAD device simulator. In addition, the simulation has been performed for finding analog performances of the proposed device as compared with conventional device. The significant improvement in drain current, Ion/Ioff ratio, output conductance and gm/Ids have been observed. Hence, the simulation results shows that the proposed device is best suitable for faster switching and low power applications.

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References

  1. 1.

    Kumar P, Bhowmick B (2017) 2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET. Superlattices Microstruct. https://doi.org/10.1016/j.spmi.2017.06.001

  2. 2.

    Kumar MJ, Reddy GV (2005) Diminished short channel effects in nanoscale double-gate silicon-on-insulator metal–oxide–semiconductor field-effect-transistors due to induced back-gate step potential. Jpn J Appl Phys 44:6508

    CAS  Article  Google Scholar 

  3. 3.

    Liu H-X, Li J, Li B, Cao L, Yuan B (2011) Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs. Chin Phys B 20:017301. https://doi.org/10.1088/1674-1056/20/1/017301

    CAS  Article  Google Scholar 

  4. 4.

    Dubey S, Santra A, Saramekala G, Kumar M, Tiwari PK (2013) An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs. IEEE Trans Nanotechnol 12:766–774. https://doi.org/10.1109/TNANO.2013.2273805

    CAS  Article  Google Scholar 

  5. 5.

    Munteanu D, Autran JL, Harrison S, Nehari K, Tintori O, Skotnicki T (2005) Compact model of the quantum short-channel threshold voltage in symmetric double-gate MOSFET. Mol Simul 31:831–837. https://doi.org/10.1080/08927020500313995

    CAS  Article  Google Scholar 

  6. 6.

    Singh K, Kumar M, Goel E, Singh B, Dubey S, Kumar S, Jit S (2016) Analytical modeling of potential distribution and threshold voltage of gate underlap DG MOSFETs with a source/drain lateral Gaussian doping profile. J Electron Mater 45:2184–2192. https://doi.org/10.1007/s11664-015-4254-y

    CAS  Article  Google Scholar 

  7. 7.

    Kumar P, Bhowmick B (2017) 2-D analytical modeling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET. J Comput Electron. https://doi.org/10.1007/s10825-017-1011-x

  8. 8.

    Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans Electron Devices 63:966–973. https://doi.org/10.1109/TED.2016.2520096

    CAS  Article  Google Scholar 

  9. 9.

    Goel E, Singh B, Kumar S, Singh K, Jit S (2017) Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs. Indian J Phys 91:383–390. https://doi.org/10.1007/s12648-016-0918-6

    CAS  Article  Google Scholar 

  10. 10.

    Sharma RK, Gupta R, Gupta M, Gupta RS (2009) Dual-material double-gate SOI n-MOSFET: gate misalignment analysis. IEEE Trans Electron Devices 56:1284–1291. https://doi.org/10.1109/TED.2009.2019695

    CAS  Article  Google Scholar 

  11. 11.

    Lin X, Feng C, Zhang S, Ho W-H, Chan M (2004) Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film. Solid State Electron 48:2315–2319. https://doi.org/10.1016/j.sse.2004.04.015

    CAS  Article  Google Scholar 

  12. 12.

    Reddy GV, Kumar MJ (2005) A new dual-material double-gate (DMDG) nanoscale SOI MOSFET—two-dimensional analytical modeling and simulation. IEEE Trans Nanotechnol 4:260–268. https://doi.org/10.1109/TNANO.2004.837845

    Article  Google Scholar 

  13. 13.

    Yin C, Chan PCH (2005) Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs. IEEE Trans Electron Devices 52:85–90. https://doi.org/10.1109/TED.2004.841349

    Article  Google Scholar 

  14. 14.

    Gupta RS, Goel K, Saxena M, Gupta M, Physics Based Modeling and Simulation of Hetero Material Asymmetric Gate Stack Epi (HEMAGASE)-MOSFET. APMC conference, 2006 doi:https://doi.org/10.1109/APMC.2005.1606400

  15. 15.

    Goel K, Saxena M, Gupta M, Gupta RS (2007) Unified model for physics-based modelling of a new device architecture: triple material gate oxide stack epitaxial channel profile (TRIMGAS Epi) MOSFET. Semicond Sci Technol 22:435–446. https://doi.org/10.1088/0268-1242/22/4/025

    CAS  Article  Google Scholar 

  16. 16.

    Kumar P, Bhowmick B (2018) Suppression of ambipolar conduction and investigation of RF performance characteristics of gate-drain underlap SiGe Schottky barrier field effect transistor. Micro Nano Lett 13:626–630. https://doi.org/10.1049/mnl.2017.0895

    CAS  Article  Google Scholar 

  17. 17.

    Sentaurus Device User Guide Version C-2009.12, Synopsys, Mountain View, CA, USA, 2009

  18. 18.

    Kumar P, Arif W, Bhowmick B (2018) Scaling of dopant segregation Schottky barrier using metal strip buried oxide MOSFET and its comparison with conventional device. Silicon 10:811–820. https://doi.org/10.1007/s12633-016-9534-5

    CAS  Article  Google Scholar 

  19. 19.

    Tripathi S (2014) A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET. Chin Phys B 23:118505. https://doi.org/10.1088/1674-1056/23/11/118505

    Article  Google Scholar 

  20. 20.

    Kumar MJ, Chaudhry A (2004) Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans Electron Devices 51:569–574. https://doi.org/10.1109/TED.2004.823803

    CAS  Article  Google Scholar 

  21. 21.

    Suveetha Dhanaselvam P, Balamurugan NB (2013) Analytical approach of a nanoscale triple-material surrounding gate (TMSG) MOSFETs for reduced short-channel effects. Microelectron J 44:400–404. https://doi.org/10.1016/j.mejo.2013.02.013

    Article  Google Scholar 

  22. 22.

    Kumar P, Bhowmick B (2018) Comparative analysis of hetero gate dielectric hetero structure tunnel FET and Schottky barrier FET with n+ pocket doping for suppression of ambipolar conduction and improved RF/linearity. J Nanoelectron Optoelectron. https://doi.org/10.1166/jno.2018.2488

  23. 23.

    Vinod A, Kumar P, Bhowmick B (2019) Impact of ferroelectric on the electrical characteristics of silicon–germanium based heterojunction Schottky barrier FET. Int J Electron Commun (AEÜ):257–263. https://doi.org/10.1016/j.aeue.2019.05.030

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Correspondence to R. Kiran Kumar.

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Kiran Kumar, R., Shiyamala, S. A 2-D Analytical Modeling of Dual Work Function Metal Gate MOSFET Using High-K Gate Dielectric with Enhanced RF/Analog Performance for Low Power Applications. Silicon 12, 2065–2072 (2020). https://doi.org/10.1007/s12633-019-00290-7

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Keywords

  • 2-D Poisson’s equation
  • Dual work function gate
  • Short channel effects
  • Drain induced barrier lowering(DIBL)
  • High -k