Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness

Abstract

In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions of linearity parameters confirm the novelty of the device and also enable us to achieve better the analog/RF applications. This promising device has an advantage of showing higher cut-off frequency, reduced DIBL, better gate oxide reliability and limiting the effects of parasitic bipolar phenomenon. In this paper we have studied the detail analysis of important linearity parameters of this proposed device with respect to change in high K oxide thickness (toxh) to have clear ideas on different linearity parameters like VIP2, VIP3, IIP3 and IMD3 and their variations. The simulated results validate that the change in toxh of this device plays a significant role on improving the linearity performance and there by careful optimization of this parameters can infer achieving better and reliable analog/linearity performances for SOC applications.

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Acknowledgments

The authors would like to express their thanks and gratitude to Brainware University, Barasat, Kolkata 700124 and Silicon Institute of Technology, Patia Hills, Bhubaneswar 751024 respectively for their valuable support and cooperation for carrying out this research work.

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Correspondence to Sarosij Adak.

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Swain, S.K., Das, S.K. & Adak, S. Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness. Silicon 12, 1567–1574 (2020). https://doi.org/10.1007/s12633-019-00257-8

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Keywords

  • High-K oxide thickness
  • Graded channel gate stack
  • Analog applications
  • RF performances
  • Linearity behavior