In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions of linearity parameters confirm the novelty of the device and also enable us to achieve better the analog/RF applications. This promising device has an advantage of showing higher cut-off frequency, reduced DIBL, better gate oxide reliability and limiting the effects of parasitic bipolar phenomenon. In this paper we have studied the detail analysis of important linearity parameters of this proposed device with respect to change in high K oxide thickness (toxh) to have clear ideas on different linearity parameters like VIP2, VIP3, IIP3 and IMD3 and their variations. The simulated results validate that the change in toxh of this device plays a significant role on improving the linearity performance and there by careful optimization of this parameters can infer achieving better and reliable analog/linearity performances for SOC applications.
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Sarkar A, Das AK, De S, Sarkar CK (2012) Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J 43(11):873–882
Ghosh S, Koley K, Sarkar CK (2015) Impact of the lateral straggle on the analog and RF performance of TFET. Microelectron Reliab 55(2):326–331
Taur Y, Liang X, Wang W, Lu H (2004) A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Letters 25(2):107–109
Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T (1987) Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Letters 8(9):410–412
Kranti A, Armstrong GA (2006) Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics. Semicond Sci Technol 21(12):1563–1572
Kim SD, Park CM, Woo JC (2002) Advanced source/drain engineering for box-shaped ultra shallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS. IEEE Transactions on Electron Devices 49(10):1748–1754
Chen, C.L., Knecht, J.M., Kedzierski, J., Chen, C.K., Gouker, P.M., Yost, D.R., Healey, P., Wyatt, P.W. and Keast, C.L., 2009, October. Channel engineering of SOI MOSFETs for RF applications. In 2009 IEEE International SOI Conference (pp. 1–2). IEEE
Ohata A (2004) Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs. Solid State Electron 48(2):345–349
Djeffal F, Meguellati M, Benhaya A (2009) A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E: Low-Dimensional Systems and Nanostructures 41(10):1872–1877
Djeffal F, Ghoggali Z, Dibi Z, Lakhdar N (2009) Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges. Microelectron Reliab 49(4):377–381
Vogel EM, Ahmed KZ, Hornung B, Henson WK, McLarty PK, Lucovsky G, Hauser JR, Wortman JJ (1998) Modeled tunnel currents for high dielectric constant dielectrics. IEEE Transactions on Electron Devices 45(6):1350–1355
Hu, C., 1996, December. Gate oxide scaling limits and projection. In International Electron devices meeting (pp. 319–322)
Reddy GV, Kumar MJ (2004) Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study. Microelectron J 35(9):761–765
Pavanello MA, Martino JA, Dessard V, Flandre D (2000) An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochem Solid-State Lett 3(1):50–52
Kilchytska V, Neve A, Vancaillie L, Levacq D, Adriaensen S, van Meer H, De Meyer K, Raynaud C, Dehan M, Raskin JP, Flandre D (2003) Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Transactions on Electron Devices 50(3):577–588
Kaya S, Ma W (2004) Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Letters 25(5):308–310
Bentrcia T, Djeffal F, Chahdi M (2013) An analytical two dimensional subthreshold behavior model to study the nanoscale GCGS DG Si MOSFET including interfacial trap effects. Microelectron Reliab 53(4):520–527
Lyu J, Park BG, Chun K, Lee JD (1997) Reduction of hot-carrier generation in 0.1-μm recessed channel nMOSFET with laterally graded channel doping profile. IEEE Electron Device Letters 18(11):535–537
Swain SK, Adak S, Sharma B, Pati SK, Sarkar CK (2015) Effect of channel thickness and doping concentration on sub-threshold performance of Graded Channel and gate stack DG MOSFETs. J Low Power Electronics 11(3):366–372
Swain SK, Dutta A, Adak S, Pati SK, Sarkar CK (2016) Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs. Microelectron Reliab 61:24–29
Adak S, Swain SK, Dutta A, Rahaman H, Sarkar CK (2016) Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DG-MOSFETs. Nano 11(09):1650101
Kumar SP, Agrawal A, Chaujar R, Gupta RS, Gupta M (2011) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron Reliab 51(3):587–596
Adak S, Swain SK, Pardeshi H, Rahaman H, Sarkar CK (2017) Effect of barrier thickness on linearity of underlap AlInN/GaN DG-MOSHEMTs. Nano 12(01):1750009
Semiconductor Industry Association, International Technology Roadmap for Semiconductors,SIA San Jose
Synopsys. TCAD Sentaurus device user's manual VG-2013.06
Aggarwal R, Agrawal A, Gupta M, Gupta RS (2011) Improved linearity performance of AlGaN/GaN MISHFET over conventional HFETs: an optimization study for wireless infrastructure applications. Superlattice Microst 50(1):1–13
Biswas K, Sarkar A, Sarkar CK (2015) Impact of barrier thickness on analog, RF and linearity performance of nanoscale DG heterostructure MOSFET. Superlattice Microst 50(1):95–104
The authors would like to express their thanks and gratitude to Brainware University, Barasat, Kolkata 700124 and Silicon Institute of Technology, Patia Hills, Bhubaneswar 751024 respectively for their valuable support and cooperation for carrying out this research work.
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Swain, S.K., Das, S.K. & Adak, S. Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness. Silicon 12, 1567–1574 (2020). https://doi.org/10.1007/s12633-019-00257-8
- High-K oxide thickness
- Graded channel gate stack
- Analog applications
- RF performances
- Linearity behavior