Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications

Abstract

This work reports a platinum silicide (PtSi) Schottky Barrier (SB) p-MOSFET (SB p-MOSFET) using charge plasma concept for low power applications. Here, we use two different materials to form source of the device. The source consists of two parts as primary source and extension. To consist source, PtSi and for extension, platinum metal is used. The proposed device is named as charge plasma (CP) SB p-MOSFET (CP SB p-MOSFET). The use of platinum extension induces the hole plasma near the source end. As a result, increased band bending reduces the SB width. This enhances the DC performance of the device. In addition, we have compared the DC and analog/RF performance of both the proposed device and the conventional SB p-MOSFET. It is observed that the proposed device exhibits improvement in on-state current (Ion), on- to off current ratio (ION/IOFF), transconductance (gm), cut-off frequency (ft), product of gain and bandwidth (fa) and transconductance generation factor (gm/Ids). We also optimized the performance of the device by modulating the work function and length of metal employed for extension. Moreover, the proposed device eliminated the doping, lowers the thermal budget requirement and unaffected from fluctuations due to randomly distributed dopant.

This is a preview of subscription content, log in to check access.

References

  1. 1.

    Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7):1725–1733

    CAS  Article  Google Scholar 

  2. 2.

    Doria RT, Pavanello MA, Trevisoli RD, de Souza M, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge JP (2011) Junctionless multiple-gate transistors for analog applications. IEEE Trans. Electron Devices 58(8):2511–2519

    CAS  Article  Google Scholar 

  3. 3.

    Gopalakrishnan K, Grin PB, Plummer JD (2002) I-MOS: A novel semi-conductor device with a subthreshold slope lower than kT/q, international Electron devices meeting, San Francisco, CA, USA, pp. 8–11

  4. 4.

    Chau R (2005) Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Electron Devices 4(2):153–158

    Google Scholar 

  5. 5.

    Priya GL, Balamurugan NB (2019) New dual material double gate junctionless tunnel FET: subthreshold modeling and simulation. Int J Electron Commun 99:130–138

    Article  Google Scholar 

  6. 6.

    Gracia D, Nirmal D, JackulineMoni D (2018) Impact of leakage cur-rent in germanium channel based DMDG TFET using drain-gate underlap technique. Int J Electron Commun 96:164–169

    Article  Google Scholar 

  7. 7.

    Kale S, Banchhor S, Kondekar PN (2015) Performance study of high-k gate and spacer dielectric dopant segregated Schottky barrier SOI MOSFET, 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India, 1142–1145

  8. 8.

    Chaudhry A, Kumar MJ (2004) Controlling short-channel e ects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4(1):99–109

    Article  Google Scholar 

  9. 9.

    Khaki rooz A et al., (2010) Fully depleted extremely thin SOI for mainstream 20 nm low-power technology and beyond, In IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC) 152–153

  10. 10.

    Chiang M-H, Lin J-N, Kim K, Chuang C-T (2007) Random dopant fluctuation in limited-width FinFET technologies. IEEE Trans. Electron Devices 54(8):2055–2060

    CAS  Article  Google Scholar 

  11. 11.

    Afzalian A, Flandre D (2012) Discrete random dopant fluctuation impact on nanoscale dopant-segregated Schottky-barrier nanowires. IEEE Electron Device Lett. 33:1228–1230

    CAS  Article  Google Scholar 

  12. 12.

    Ostling M, Luo J, Gudmundsson V, Hellstrom P-E, Malm BG (2010) Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts, in Proc 27th Int Conf Microelectron (MIEL) 9–13

  13. 13.

    Jhaveri R, Nagavarapu V, Woo JCS (2009) Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications. IEEE Trans. Electron Devices 56(1):93–99

    CAS  Article  Google Scholar 

  14. 14.

    Jhaveri R, Woo JCS (2006) Schottky tunneling source MOSFET design for mixed mode and analog applications, in proc. 36th Eur. Solid-state Device res. Conf., Montreux, Switzerland 295–298

  15. 15.

    Kale S, Kondekar PN (2017) Design and investigation of dielectric engineered dopant segregated Schottky barrier MOSFET with NiSi source/drain. IEEE Trans. Electron Devices 64(11):4400–4407

    CAS  Article  Google Scholar 

  16. 16.

    Guin S, Chattopadhyay A, Karmakar A, Mallik A (2014) Impact of a pocket doping on the device performance of a Schottky tunneling field effect transistor. IEEE Trans. Electron Devices 61(7):2515–2522

    CAS  Article  Google Scholar 

  17. 17.

    Afzalian A, Flandre D (2011) Computational study of dopant segregated nanoscale Schottky barrier MOSFETs for steep slope, low SD-resistance and high on-current gate modulated resonant tunneling FETs. Solid State Electron 65(1):123–129

    Article  Google Scholar 

  18. 18.

    Larson JM, Snyder JP (2006) Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans Electron Dev 53(5):1048–1058

    CAS  Article  Google Scholar 

  19. 19.

    Kale S, Kondekar PN (2016) Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: proposal and investigation. Superlattices Microstructures 89:225–230

    CAS  Article  Google Scholar 

  20. 20.

    Z. Zhang, Z. Qiu, P.-E. Hellstrm Hellstrom, G. Malm, J. Olsson, J. Lu, M. stling, S.-L. Zhang, SB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant segregation, 29(1) (2008) 125–127

  21. 21.

    Choi C-j, Jang M-g, Kim Y-y, Jun M-s, Kim T-y, Lee S-j (2008) Platinum silicided PtSi Schottky barrier metal-oxide-semiconductor field-effect transistors scaled down to 20 nm. Electron Lett 44(2):159–160

    CAS  Article  Google Scholar 

  22. 22.

    G. Larrieu, E. Dubois, Integration of PtSi-based Schottky-barrier p-MOSFETs with a midgap tungsten gate, 52(12) (2005) 2720–2726

  23. 23.

    Kinoshita A, Tsuchiya Y, Yagishita A, Uchida K, Koga J (2004) Solu-tion for high performance Schottky-source/drain MOSFETs: Schottky-barrier height engineering with dopant-segregation technique, in VLSI Symp. Tech. Dig., pp. 168–169

  24. 24.

    Knoch J, Zhang M, Zhao T, Lenk SS (2005) E effctive Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistor using dopant segregation. Appl Phys Lett 87(26):263505–263507

    Article  Google Scholar 

  25. 25.

    Kale S, Kondekar PN (2015) Design and investigation of double gate Schottky barrier MOSFET using gate engineering. Micro and Nano Lett. 10(12):707–711

    CAS  Article  Google Scholar 

  26. 26.

    Lide DR, (2008) CRC Handbook on Chemistry and Physics, 89th ed. New York: Taylor and Francis, pp. 12–114

  27. 27.

    Hueting RJE, Rajasekharan B, Salm C, Schmitz J (2008) The charge plasma P-N diode. IEEE Electron Device Lett. 29(12):1367–1369

    Article  Google Scholar 

  28. 28.

    Kumar MJ, Nadda K (2012) Bipolar charge-plasma transistor: a novel three terminal device. IEEE Trans. Electron Devices 59(4):962–967

    CAS  Article  Google Scholar 

  29. 29.

    Device Simulation Software ATLAS (2014) Santa Clara. CA, USA

    Google Scholar 

  30. 30.

    Ieong M, Solomon PM, Laux SE, Wong H-SP, Chidambarrao D (Dec. 1998) Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model. Electron devices meeting, 1998. IEDM '98. Technical digest., international, pp.733–736, 6–9

    Google Scholar 

  31. 31.

    Matsuzawa K, Uchida K, Nishiyama A (2000) A Uni ed Simulation of Schottky and Ohmic contacts. IEEE Trans. Electron Dev. 47(01):103–108

    CAS  Article  Google Scholar 

  32. 32.

    Kale S, Kondekar PN (2015) Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering. Electron Lett. 51(19):1536–1538

    CAS  Article  Google Scholar 

  33. 33.

    Kale S, Kondekar PN (2015) Ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFET. IETE J Res 61(4):323–328

    Article  Google Scholar 

  34. 34.

    Vega RA, Liu TJK (2008) A comparative study of dopant-segregated Schottky and raised source/drain double-gate MOSFETs. IEEE Trans. Electron Dev 55(10):2665–2677

    Article  Google Scholar 

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to S. Kale.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Kale, S. Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications. Silicon 12, 479–485 (2020). https://doi.org/10.1007/s12633-019-00161-1

Download citation

Keywords

  • Schottky barrier
  • Charge plasma
  • Platinum silicide
  • Random dopant fluctuations