Optimization of CMOS repeater driven interconnect RC line using genetic algorithm



In this work, optimization of complementary metal oxide semiconductor (CMOS) repeater driven interconnect resistive-capacitive (RC) line is carried out using genetic algorithm (GA). This work is aimed at powerdelay- product (PDP) minimization of RC interconnect at 180 nm technology node. The algorithm simultaneously optimizes the values of supply voltage, number of repeaters and repeater width for delay and PDP minimization. The accuracy of results obtained is verified by simulations from Cadence virtuoso tool. For delay minimization, comparison of GA results with previous results of the literature shows an improvement of 44.4% in the value of the optimal number of repeaters required. This improvement is obtained by increasing the repeater size, which also increases power dissipation, so a tradeoff has also been achieved in terms of PDP minimization. The comparison of PDP results obtained in this work, with the results at 70, 100, and 130 nm technologies from literature shows improvement in optimal number of repeaters required. The results of algorithm and simulations are in good agreement and demonstrate the validity of proposed algorithm.

Key words

complementary metal oxide semiconductor (CMOS) genetic algorithm interconnects optimal power-delay-product repeater 

CLC number

TP 333 

Document code


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    BANERJEE K, MEHROTRA A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs [J]. IEEE Transactions on Electron Devices, 2002, 49(11): 2001–2007.CrossRefGoogle Scholar
  2. [2]
    CHANDEL R, SARKAR S, AGARWAL R P. An analysis of interconnect delay minimization by low-voltage repeater insertion [J]. Microelectronics Journal, 2007 38: 649–655.CrossRefGoogle Scholar
  3. [3]
    HAVEMANN R H, HUTCHBY J A. Highperformance interconnects: An integration overview [J]. Proceedings of the IEEE, 2001, 89(5): 586–601.CrossRefGoogle Scholar
  4. [4]
    ADLER V, FRIEDMAN E G. Repeater design to reduce delay and power in resistive interconnects [J]. IEEE Transactions on Circuits and Systems. II: Analog and Digital Signal Processing, 1998, 45(5): 607–616.CrossRefGoogle Scholar
  5. [5]
    RABEY J M. Digital integrated circuits: A design perspective [M]. 2nd ed. India: Prentice Hall of India, 2002: 134–172.Google Scholar
  6. [6]
    ABOU-SEIDO A I, NOWAK B, CHU C. Fitted Elmore delay: A simple and accurate interconnect delay model [J]. IEEE Transactions on VLSI Systems, 2004: 1–7.Google Scholar
  7. [7]
    CHANDEL R, RAO S. Optimal design of repeaters using GA for VLSI interconnects [J]. International Journal of Information and Telecommunication Technology, 2012, 4(1): 5–11.Google Scholar
  8. [8]
    MUI M L, BANERJEE K, MEHROTRA A. A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation [J]. IEEE Transactions on Electron Devices, 2004, 51(2): 195–203.CrossRefGoogle Scholar
  9. [9]
    ISMAIL Y I, FRIEDMAN E G. Optimum repeater insertion based on a CMOS Delay model for on-chip RLC interconnect [C]//Proceedings of 11th Annual IEEE International ASIC Conference. [s.l.]: IEEE, 1998: 369–373.Google Scholar
  10. [10]
    NARASIMHAN A, SRIDHAR R. Variability aware low-power delay optimal buffer insertion for global interconnects [J]. IEEE Transactions on Circuits and Systems. I: Reg Papers, 2010, 57(12): 3055–3063.MathSciNetCrossRefGoogle Scholar
  11. [11]
    MEHRI M, SARVARI R, KOUHANI M H M, et al. VLSI interconnect issues in definitive and stochastic environments [J]. Microelectronics Journal, 2015, 46(5): 351–361.CrossRefGoogle Scholar
  12. [12]
    CORTéS-HERNáNDEZ D M, TORRES-TORRES R, LINARES-ARANDA M, et al. Piecewise physical modeling of series resistance and inductance of on-chip interconnects [J]. Solid-State Electronics, 2016, 120: 1–5.CrossRefGoogle Scholar
  13. [13]
    ALIOTO M. Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools [J]. Microelectronics Journal, 2011, 42: 63–73.CrossRefGoogle Scholar
  14. [14]
    MANIPATRUNI S, LIPSON M, YOUNG I A. Device scaling considerations for nanophotonic CMOS global interconnects [J]. IEEE Journal of Selected Topics in Quantum Electronics, 2013, 19(2): 8200109.CrossRefGoogle Scholar
  15. [15]
    MAHESHWARI V, MUKHERJEE S, KAR R, et al. Analytical crosstalk modelling of on-chip RLC global interconnects with skin effect for ramp input [J]. Procedia Technology, 2012; 6: 814–821.CrossRefGoogle Scholar
  16. [16]
    KUHN K J. Considerations for ultimate CMOS scaling [J]. IEEE Transactions on Electron Devices, 2012, 59(7): 1813–1828.CrossRefGoogle Scholar
  17. [17]
    GORE C, BRITTO F, RAJE M. Genetic algorithms in VLSI floorplanning [J]. International Journal of Engineering Research & Technology, 2012, 1(8): 1–7.Google Scholar
  18. [18]
    SILLA C N. Teaching genetic algorithm-based parameter optimization using Pacman [C]//Proceedings of Frontiers in Education Conference (FIE). [s.l.]: IEEE, 2016: 1–6.Google Scholar
  19. [19]
    SASTRY K, GOLDBERG D, KENDALL G. Genetic algorithm [M]//BURKE E, KENDALL G. Search Methodologies: Introductory Tutorials in Optimization and Decision Support Techniques. USA: Springer, 2005: 97–125.CrossRefGoogle Scholar
  20. [20]
    HOUCK C R, JOINES J A, KAY M G. A genetic algorithm for function optimization: A Matlab implementation [R]. Raleigh: North Carolina State University, 1995.Google Scholar
  21. [21]
    KHANNA G. Optimal design and mitigation of non ideal effects in VLSI interconnects [D]. Hamirpur, India: National Institute of Technology, 2012.Google Scholar

Copyright information

© Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg 2017

Authors and Affiliations

  • Jasmeet Kaur
    • 1
  • Sandeep Singh Gill
    • 1
  • Navneet Kaur
    • 1
  1. 1.Department of Electronics and Communication EngineeringGuru Nanak Dev Engineering CollegeLudhianaIndia

Personalised recommendations