The microelectronics circuits used in the aerospace applications work in an extremely radiated environment, causing a large possibility of a single event upset (SEU). Static random access memory (SRAM) is the most susceptible of these circuits as it occupies a significant area of the recent System-on-Chip (SoC) and also frequently store important data. Therefore, retaining data integrity with regards to SEUs has become a primary requirement of SRAM bit-cell design. Use of FinFET devices in the SRAM cell can offer higher resistance against radiation compared to the CMOS counterparts. In this work, using TCAD simulations, we have analysed effect of SEU on three different FinFET based 6T bit-cell configurations, in which number of fins in the access and pull-down transistors are different. We have analysed the effect of SEU at an angle of 90° and 60°.
A Single Event Upsets (SEUs) is change of state in micro-electronics devices caused by striking of ionizing particle (ions, electrons, protons, etc.) at a sensitive node of a device . Continuous transistor scaling and lowering VDD at each successive node exacerbates this effect, as the volume of charge stored in a storage node is becoming gradually smaller due to smaller node capacitance and lower VDD . This makes microelectronics devices more vulnerable to SEU. The possibility of a radiation particle strike on a Static Random Access Memory (SRAM) is relatively high because of its significant share in the overall chip area of a System-on-Chip . In addition, as the device size reduces, separation between adjacent circuit nodes decreases drastically and the effect of multiple-node upset due to charge sharing is more severe .
The traditional 6T SRAM cell employs a regenerative feedback loop between two opposite inverters to hold the latched data. However, the 6T cell is susceptible to SEU, since the upset that causes voltage level of one of the storage node to cross the tripping point of the opposite inverter will cause a data flip. Importantly, this data failure rate raises with technology advancement .
Technology level solutions, like use of silicon-on insulator (SOI) can enhance the data reliability against SEU by reducing SEU-sensitive volume . However, SEU-sensitive volume can be further reduced by using SOI FinFET devices in the SRAM design, which can offer higher immunity against SEU compared to the bulk CMOS counterparts . Hence, 6T SRAM cell design using SOI FinFETs is more resistant against radiation effect compared to that of design using MOSFET counterpart. Besides, FinFET based SRAM cells usually employ different numbers of fin in the cell transistors to improve performance metrics of read and write operations . Hence, it is absolutely essential to analyse an effect of SEU in various FinFET based 6T SRAM cell configurations containing different fins in the cell transistors.
In this work, using TCAD simulations, we have analysed effect of SEU on SOI FinFET based 6T SRAM cell configurations. We have characterized three different SRAM cell configurations, in which numbers of fins of access and pull-down transistors of 6T cell are different. In addition, as the effect of SEU in the cell structure depends on incident angle of striking particle . In this work, we have analysed the effect of SEU in the 6T cell at angle of 90° and 60°.
Figure 1 depicts a SOI tri-gated FinFET in which three gate electrodes covered around the thin fin region. This arrangement helps to achieve higher controllability of the gate electrodes over the channel region. This in turn helps to improve ION/IOFF ratio and craft FinFET as an ideal candidate for low voltage SRAM bit-cell design [4, 5]. Additionally, SEU-sensitive volume is reduced by using FinFET devices in the SRAM cell design and can offer higher resistance against SEU compared to the bulk CMOS counterparts [8,9,10].
FinFET based 6T SRAM cell
6T SRAM cell can store single bit data using two cross-coupled inverters as shown in figure 2. The fundamental three operations in 6T SRAM cell are read, write and hold.
The word line (WL) is connected to the ground. Accordingly, M5 and M6 are turned off and isolate the latching part from two bit lines. Hence, M1, M2, M3 and M4 formed latching structure and hold a stored data bit as long as they disconnected from the bit-lines.
In this operation, bit-lies are pre-charged to VDD and the WL is also connected to the VDD as shown in figure 3.
In this situation, transistors M5 and M6 are tuned ON. As per data conditions Q = “1” and Qbar = “0”, M1 and M4 are turned off and M3 and M2 are turned on. Hence, bit-line current will flow through BLB-M6-M2 as shown in figure 3. Accordingly, voltage level of bit-line BLB discharges and voltage level of BL maintains at VDD.
The voltage levels of bit-lines are opposite to each other as shown in figure 4 and the WL is connected to VDD. This will turn ON the transistors M5 and M6. In this situation, the voltage level of node Q drops and the voltage level of node Qbar raises until the voltage level of Q will be adequate to turn on M4 and turn off M2 or the voltage level at node Qbar will be adequate to turn on M3 and turn off the M1. Subsequently, the voltage level of Qbar and Q will be turned over to ‘1’ and ‘0’, respectively.
Effect of SEU in 6T SRAM cell
As per the data condition (Q = 1, Qbar = 0) shown in figure 5, transistor M1 and M4 are in the off states. If a particle strikes on the drain region of off-state transistor M1, the drain regions begin to collect charges due to particle striking on the space-charge region located in reverse biased p-n junction. Consequently, a negative transient pulse is generated at node Q. If the reduced voltage level at node Q is sufficiently low enough to turn ON M4, the data condition at storage nodes changes to Q = 0 and Qbar = 1 as shown in figure 5. This is referred as SEU.
Effect of SEU in FinFET based SRAM cell configurations containing different number of fins
In order to ensure successful read and write operations, the sizing ratio of the pull down transistors to that of access transistor should be greater than 1 and the sizing ratio of pull-up transistor to the access transistor should be less than 1 [10, 11]. To satisfy such non uniform sizing requirements, FinFET based SRAM cells usually occupy different numbers of fin in the cell transistors as shown in table 1, which leads to three different configurations (Cell 1, Cell 2 and Cell 3).
As the number of fins increases in the cell transistor, charge collection volume of the cell transistor increases. When particle strike on any sensitive node of circuitry, then charge is scattered to the fins and as a result effect of SEU become less. As a result, effect of SEU is different in SRAM cells containing different fins (Cell 1, Cell 2 and Cell 3 as per table 1). Hence, it is essential to analyze an effect of SEU in 6T SRAM cells containing different fins.
However, very limited literatures are available in which FinFET based 6T SRAM cell was analysed in light of SEUs. Besides, no study was reported in the literatures in which effect of SEU is analysed on FinFET based 6T SRAM cells containing different fins. For that reason, we analyse the effect of SEU on SOI FinFET based 6T SRAM cell containing different fins (Cell 1, Cell 2 and Cell 3 as per table 1) using 3D TCAD tool.
The simulation methodology used during this work is as shown in figure 6 . TCAD simulation is initiated by running process rules on GDSII mask layout. Gds2mesh tool generates 3D device based on layout and process rules. Radiation effect is generated and applied to 3D device with help of visual particle tool. Genius simulator is used to simulate 3D device.
Various SOI FinFET based 6T SRAM cells containing different fin configurations (Cell 1, 2 and 3) are implemented as shown in figure 7. The device dimension and electrical parameters used during simulations are listed in table 2. The post-layout simulations are performed on various 6T SRAM cell configurations.
Results and discussion
In this section, in the beginning, we demonstrate functionality correctness of various 6T cells taken into considerations. Then we analyse effect of SEU on cells by striking the particles at an angle of 90° and 60°.
Functionality correctness of various cells for read and write operation
The TCAD simulation result shown in figure 8 indicates the functionality of the various bit-cells for read-1 operation (Q = ‘1’ and Qbar = ‘0’). As shown in figure 8, voltage level of bit-line BLB is reduced in all the cells. While voltage level of bit-line BL is maintained at VDD. This in turn indicates the functionality correctness of various bit-cells for read-1 operation. As it can be seen from figure 8, bit-line BLB of cell 3 takes smaller time to discharge compared to cell 1 and 2. This is due to the fact that bit line discharging path of cell 3 is much faster compared to cell 1 and 2. The bit line discharging path of cell 3 is faster, since it contains higher fins in the pull-down transistor compared to that of cell 1 and cell 2.
As shown in figure 9, to perform write-0 operation, assumed data condition of SRAM cell is Q = “1” and Qbar = ‘0’. As it can be seen from figure 9 that cell 2 take less time to perform write operation compared to cell 1 and 3. Since in cell 2, access and pull down transistors employ 2 fins, which help to increase the writing speed.
Analysis of SEU effect for particle strike at an angle 90°
In view of fact that probability of SEU is higher during hold operation compared to read and write operation in the given SRAM cell. SRAM cells (Cell 1, Cell 2 and Cell 3) are configured in hold state with data conditions Q = ‘1’ and Qbar = ‘0’. During hold operation, particle strike at energy of 100 MeV with angle of 90o. The particle strike at the drain of off-state transistor M1. The voltage vs. time graph obtained using Visual TCAD software is as shown in figure 10.
As shown in figure 10, due to the effect of SEU, data is flipped at node Q and Qbar in cell 1 and cell 2. While, data conditions (voltage level) at node Q and Qbar do not flipin cell 3. It can be seen from the figure that voltage level at node Qbar is not much affected in cell 3 as compared to that of cells 1 and 2. This is due to the fact that pull down transistor of cell 3 consists of higher fins compared to that of cell 1 and 2. This in turn helps to maintain voltage level at node Qbar. Subsequently, voltage level at node Q recovered to its initial value and data was not flipped in cell 3.
Analysis of SEU effect for particle strike at an angle 60°
In this experiment, particle strikes at energy of 100 MeV but with an angle of 60o. SRAM cells (Cell 1, Cell 2 and Cell 3) are configured in hold state with data conditions Q = ‘1’ and Qbar = ‘0’. The voltage vs. time graph obtained using Visual TCAD software is as shown in figure 11.
As shown in figure 11, like previous case, due to effect of SEU, data is flipped at node Q and Qbar in cell 1 and 2. While, data conditions at node Q and Qbar is recovered and does not flipped in cell 3. However, as shown in figure 11, that voltage level at node Qbar is more degraded at an angle of 60° compared to 90° in all the cells. Since particle strikes at an angle 60° affects more than one transistor so charge collection is increased and subsequently voltage level of node Qbar is more degraded. Results of above experiments related to SEU indicate that Cell 3 is more immune against SEU compared to cell 1 and cell 2. Hence, it is essential to analyze the effect of SEU in cell 3 at higher energy.
Effect of SEU in cell 3 for particle energy at 100 MeV, 200 MeV, 300 MeV
In this experiment, particle strikes with energy level of 100 MeV, 200 MeV, 300 MeV with an angle of 90°. The voltage vs. time graph obtained using Visual TCAD software is as shown in figure 12. It can be seen that when particle strikes with energy of 300 MeV, the stored data bits at node Q and Qbar in cell 3 is flipped. Particle with higher energy level increases the charge collection at the corresponding node in the given cell, which in turn helps to flip the data condition at the storage nodes. From this experiment, it is concluded that as the number of fin increases in the pull down transistor of SRAM cell, immunity against SEU also increases in the SRAM cell.
In this work, using 3D TCAD simulations, we have analysed effect of SEU on FinFET based 6T SRAM cell configurations containing different fins in the cell transistors. We have analysed the effect of SEU at angle of 90° and 60°. It is observed that use of more number of fins in the pull-down transistor increases the immunity of the SRAM cell against radiation particles. It is also observed that use of higher fins in the pull-down transistor helped to increase the reading and writing speed.
Dodd L and Massengill L 2003 Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nucl. Sci. 50(3): 261–263
WP-01206-1.0. White Paper. © 2013 Altera Corporation, Introduction to Single-Event Upsets, San Jose, CA
Bhattacharya D and Jha N 2014 FinFETs: from devices to architectures. Adv. Electron. 10: 365689. https://doi.org/10.1155/2014/365689
Limachia M, Thakker R and Kothari N 2018 A near-threshold 10T differential SRAM cell with high read and write margin for tri-gated FinFET technology. Integr VLSI J Elsevier 61: 126–137
Senthil Kumar M 2015 A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increase read access time, 28 April 2015 Springer © Science and Business Media, New York
Saxena G, Agrawal R and Sharma S 2013 Single event upset (SEU) in SRAM. Int. J. Eng. Res. Appl. 3(4): 2171–2175
Rahman N and Singh B P 2013 Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45 nm Technology, Int. J. Comput. Appl. 66(20): 283–297 (ISSN: 0975-8887)
Kumar V, Singh R P P, Gupta R and Vaid R 2016 Effect of high-k gate dielectric materials on electrical characteristics of GaAs channel material based double gate n-FinFET. Int. J. Emerg. Res. Manag. Technol. 139: 28–32
Mustafa M, Bhat T A and Beigh M R 2013 Threshold voltage sensitivity to metal gate work-function based performance evaluation of double-gate n-FinFET structures for LSTP technology. World J. Nano Sci. Eng. 3(1): 17–22
Goyal A, Tomar A and Goyal A 2017 Effect of W/L ratio on SRAM cell SNM for high-speed application. Int. Res. J. Eng. Technol. 4(4): 2326-2332
Cogenda TCAD Tool Suite [Online]. Available: http://www.congendatcad.com
Ahlbin J R 2011 Effect of multiple-transistor charge collection on single-event transient pulse widths. IEEE Trans. Device Mater. 11(3): 401–405
Authors are thankful for the financial support offered under the Grant Number: GUJCOST/MRP/2015-16/2651 by Gujarat Council On Science and Technology (GUJCOST), Department of Science and Technology, Government of Gujarat to carry out this research activity.
About this article
Cite this article
Limachia, M., Kothari, N. Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect. Sādhanā 45, 31 (2020). https://doi.org/10.1007/s12046-020-1269-8
- Static random access memory (SRAM)
- single event upset (SEU)