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Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application

  • Physics and Biology
  • Published:
Wuhan University Journal of Natural Sciences

Abstract

QLC (Quad-Level Cell) NAND flash will be one of the future technologies for next generation memory chip after three-dimensional (3D) TLC (Triple-Level Cell) stacked NAND flash. In QLC device, data errors will easily occur because of 24 data levels in the limited voltage range. This paper studies QLC NAND technology which is 4 bits per cell. QLC programming methods based on 16 voltage levels and reading method based on “half-change” Gray coding are researched. Because of the probable error impact of QLC NAND cell’s voltage change, the solution of generating the soft information after XOR (exclusive OR) the soft bits by internal read mechanism is presented for Low-Density Parity-Check (LDPC) Belief Propagation (BP) decoding in QLC design for its system level application.

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Authors and Affiliations

  1. School of Optics and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, Hubei, China

    Shijun Liu, Xuecheng Zou & Baocun Wang

Authors
  1. Shijun Liu
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  2. Xuecheng Zou
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  3. Baocun Wang
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Corresponding author

Correspondence to Shijun Liu.

Additional information

Biography: LIU Shijun, male, Ph.D. candidate, research direction: memory and communication IC design.

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Liu, S., Zou, X. & Wang, B. Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application. Wuhan Univ. J. Nat. Sci. 23, 70–78 (2018). https://doi.org/10.1007/s11859-018-1296-z

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  • DOI: https://doi.org/10.1007/s11859-018-1296-z

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