Investigation of DC, RF and Linearity Performances of III–V Semiconductor-Based Electrically Doped TFET for Mixed Signal Applications

Abstract

The aim of this paper is to bring forward a novel hetero-material electrically doped (ED) GAA TFET for high-performing and power efficient mixed signal applications. A number of low and high band gap III–V semiconductors were considered at source and drain channel regions, and their electrical characteristics were compared to identify the best alternative. To that end, DC/RF/linearity properties of AlGaSb/GaAsP, Ge/GaAs, Si/GaAs, Si/Ge, Silicon and SiGe/Si based ED GAA TFETs were analyzed. We found that the AlGaSb/GaAs-ED-TFET provides 16 \(\mu \hbox {A}\) ON current at 25 mV/decade subthreshold swing and 1e13 \(I_{ON}/ I_{OFF}\) ratio with exceptional analog and linearity characteristics. Also, we found that interface trap charges (ITC) in AlGaSb/GaAs-ED-TFET present negligible impact and have no effect on system performance. Further, improvisation is possible through mole fraction optimization of \(Al_{x}Ga_{1-x}Sb\). Finally, the mixed signal components that are widely available in system architectures are implemented using AlGaSb/GaAs-ED-TFET and their performance criteria are measured. All device simulations were performed using the TCAD Silvaco tool, and look-up based Verilog-A technique was used for circuit simulation in Cadence.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21

References

  1. 1.

    M. Ammar, R. Giovanni, and C. Bruno, Internet of things: a survey on the security of IoT frameworks. J. Inform. Secur. Appl. 38, 8 (2018). https://doi.org/10.1016/j.jisa.2017.11.002

    Article  Google Scholar 

  2. 2.

    A. Haroon, M.A. Shah, Y. Asim, W. Naeem, M. Kamran, and Q. Javaid, Constraints in the IoT: the world in 2020 and beyond. Int. J. Adv. Comput. Sci. Appl. 7, 11 (2016). https://doi.org/10.14569/IJACSA.2016.071133.

    Article  Google Scholar 

  3. 3.

    D. Robertson, The Past, Present, and Future of Data Converters and Mixed Signal ICs: A “Universal” Model, Symposium on VLSI Circuits, Digest of Technical Papers. Honolulu. HI p. 1 (2006). https://doi.org/10.1109/VLSIC.2006.1705284.

  4. 4.

    C. Rajan, J. Patel, D. Sharma, A.K. Behera, A. Lodhi, A. Lemtur, and D.P. Samajdar, Implementation of \(\sum \triangle \) ADC using electrically doped III–V ternary alloy semiconductor nano-wire TFET. Micro Nano Lett. 15(4), 266 (2020). https://doi.org/10.1049/mnl.2019.0478.

    CAS  Article  Google Scholar 

  5. 5.

    C. Rajan and D.P. Samajdar, Performance Analysis of an Electrically Doped \(Al_{0.05}Ga_{0.95}Sb/GaAs_{0.5}P_{0.5}\) Nanowire TFET for Mixed Signal Application, 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, p. 986–990. https://doi.org/10.1109/SPIN48934.2020.9071048.

  6. 6.

    A. Lodhi, C. Rajan, D. Sharma, A.K. Behera, D.P. Samajdar, and A. Kumar, Implementation of digital-to-analog converter through CP based GaAs/GaSb nanowire GAA-TFET. Appl. Phys. A 126, 487 (2020). https://doi.org/10.1007/s00339-020-03616-0.

    CAS  Article  Google Scholar 

  7. 7.

    A. Mesgarani, M.N. Alam, F.Z. Nelson, and S.U. Ay, Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS, 53rd IEEE International Midwest Symposium on Circuits and Systems. Seattle. WA p. 893 (2010). https://doi.org/10.1109/MWSCAS.2010.5548658.

  8. 8.

    G.C. Patil and S. Qureshi, Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits. Microelectron. J. 43(5), 321 (2012). https://doi.org/10.1016/j.mejo.2011.12.015.

    CAS  Article  Google Scholar 

  9. 9.

    L.S. Wong, S. Hossain, J. Edvinsson, D.H. Rivas, and H. Naas, A very low-power CMOS mixed-signal IC for implantable pacemaker applications. IEEE J. Solid-State Circ. 39(12), 2446 (2004). https://doi.org/10.1109/JSSC.2004.837027.

    Article  Google Scholar 

  10. 10.

    J. Scholvin, D.R. Greenberg, and J.A. Alamo, Performance and limitations of 65 nm CMOS for integrated RF power applications. InIEEE InternationalElectron Devices Meeting, IEDM Technical Digest., Washington, DC, 2005, p. 369. https://doi.org/10.1109/IEDM.2005.1609353.

  11. 11.

    Y. Taur, CMOS design near the limit of scaling. IBM J. Res. Dev. 46, 213 (2002). https://doi.org/10.1147/rd.462.0213.

    Article  Google Scholar 

  12. 12.

    B.V. Chandan, K. Nigam, C. Rajan, and D. Sharma, A fair comparison of the performance of charge plasma and electrostatic tunnel FETs for low-power high-frequency applications. J. Comput. Electron. 18, 1201 (2019). https://doi.org/10.1007/s10825-019-01388-2.

    Article  Google Scholar 

  13. 13.

    S. Yadav, C. Rajan, D. Sharma, and S. Balotiya, GaAs-SiGe based novel device structure of doping less tunnel FET, VLSI design and test. In VDAT, Communications in Computer and Information Science, vol. 1066. Springer, Singapore, p. 694 (2019). https://doi.org/10.1007/978-981-32-9767-8_57.

  14. 14.

    A. Lemtur, D. Sharma, J. Patel, P. Suman, and C. Rajan, Two-stage op-amp and integrator realisation through GaAsP/AlGaSb nanowire CP-TFET. Micro Nano Lett. 14(9), 980 (2019). https://doi.org/10.1049/mnl.2018.5675.

    CAS  Article  Google Scholar 

  15. 15.

    C. Rajan, D. Sharma, and D.P. Samajdar, Implementation of physical unclonable functions using hetero junction based GAA TFET. Superlattice Microst. 126, 72 (2019). https://doi.org/10.1016/j.spmi.2018.12.010.

    CAS  Article  Google Scholar 

  16. 16.

    S. Gupta, K. Nigam, S. Pandey, D. Sharma, and P.N. Kondekar, Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET. IEEE T. Electron Dev. 64(11), 4731 (2017). https://doi.org/10.1109/TED.2017.2754297.

    CAS  Article  Google Scholar 

  17. 17.

    J. Madan and R. Chaujar, Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Dev. Mater. Reliab. 16(2), 227 (2016). https://doi.org/10.1109/TDMR.2016.2564448.

    CAS  Article  Google Scholar 

  18. 18.

    K.S. Singh, S. Kumar, and K. Nigam, Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Trans. Dev. Mater. Reliab. 20(2), 404 (2020). https://doi.org/10.1109/TDMR.2020.2984669.

    CAS  Article  Google Scholar 

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Chithraja Rajan.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Rajan, C., Samajdar, D.P. & Lodhi, A. Investigation of DC, RF and Linearity Performances of III–V Semiconductor-Based Electrically Doped TFET for Mixed Signal Applications. Journal of Elec Materi (2021). https://doi.org/10.1007/s11664-021-08753-7

Download citation

Keywords

  • Electrically doped
  • TFET
  • hetero-material
  • mixed signal