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High-level synthesis for FPGAs: code optimization strategies for real-time image processing

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Abstract

High-level synthesis (HLS) is a potential solution to increase the productivity of FPGA-based real-time image processing development. It allows designers to reap the benefits of hardware implementation directly from the algorithm behaviors specified using C-like languages with high abstraction level. In order to close the performance gap between the manual and HLS-based FPGA designs, various code optimization forms are made available in today’s HLS tools. This paper proposes a HLS source code and directive manipulation strategy for real-time image processing by taking into account the applying order of different optimization forms. Experiment results demonstrate that our approach can improve more effectively the test implementations comparing to the other optimization strategies.

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Notes

  1. DOALL loop: the loops with independent iterations.

  2. Degree of parallelism of an operation: a variable that indicates how many times an operation can be or are being simultaneously executed in maximum for an implementation.

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Acknowledgements

The authors would like to thank the China Scholarship Council, the CAS Pioneer Hundred Talents Program and the Conseil Régional de Bourgogne Franche-Comté for their funding of our studies.

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Authors and Affiliations

  1. Stat Key Laboratory of Acoustics, Institute of Acoustics, Chinese Academy of Sciences, Beijing, 100190, China

    Chao Li

  2. LE2I FRE2005 CNRS, Arts et Métiers, Univ. Bourgogne Franche-Comté, 21000, Dijon, France

    Chao Li, Yannick Benezeth, Dominique Ginhac & Fan Yang

  3. Laboratory of CPTC, Univ. Bourgogne Franche-Comté, 21000, Dijon, France

    Yanjing Bi

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  1. Chao Li
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Correspondence to Yanjing Bi.

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Li, C., Bi, Y., Benezeth, Y. et al. High-level synthesis for FPGAs: code optimization strategies for real-time image processing. J Real-Time Image Proc 14, 701–712 (2018). https://doi.org/10.1007/s11554-017-0722-3

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