Energy-aware cache hierarchy assessment targeting HEVC encoder execution

  • Eduarda MonteiroEmail author
  • Mateus Grellert
  • Bruno Zatt
  • Sergio Bampi
Original Research Paper


This article presents a framework for assessing the behavior and energy impact of cache hierarchies when encoding HEVC on general-purpose processors. The memory energy estimation framework estimates energy consumption of cache hierarchies based on mathematical models combined with memory access profiling tools. The energy analysis of several cache hierarchies targeting HEVC encoders with different input parameters is also carried out. This article provides relevant information on the energy consumption of HEVC encoders by taking into account the different tradeoffs between energy efficiency, coding efficiency, and other important cache memory design parameters, such as miss rates and access latency. The first analysis explores cache performance for different specifications, such as capacity, line size. Results show that most of the energy is spent on reading operations (almost 73% on the first level cache), indicating that HEVC encoders could benefit from memory technologies with low reading energy costs. This analysis also pointed that increasing the capacity affects more the energy performance of the first level cache, which represents 34.78% (on average) more energy consumption than the last level cache. Based on this investigation, we report the most suited cache specifications for HEVC encoders for each video resolution. The second analysis discusses the impact of HEVC input parameters in cache performance, demonstrating that it is possible to save up to 30% of energy with a small increase of 2% in BD-BR. A comparative analysis between HM (HEVC model) and x265 (H.265 video codec) HEVC software models is presented, demonstrating that x265 is faster (speedup to 648x), and more cache efficient providing less memory energy (31.38% on average) compared to the HM implementation. The results obtained with the proposed framework indicate that the management of video encoding parameters combined with application-tuned cache specifications has a high potential to reduce energy consumption of video coding systems while keeping video quality.


HEVC Video coding Energy consumption Memory access Multilevel cache memories Memory profiling 



This work was partially financed by the National Council for Scientific and Technological Development (CNPq), Coordination of Improvement of Superior Education Staff (CAPES), and Research Support Foundation of Rio Grande do Sul (FAPERGS) (Grant No. 2465-12).


  1. 1.
    Samsung Corporation: Samsung exynos processors [Online]. Accessed 04 Aug 2016 (2016)
  2. 2.
    ARM: ARM—The architecture for the digital world [Online]. Accessed 04 Aug 2016 (2016)
  3. 3.
    Asus Corporation: Asus Zenfone [Online]. Accessed 04 Aug 2016 (2016)
  4. 4.
    Intel Atom: Intel Atom Processor [Online]. Accessed 04 Aug 2016 (2016)
  5. 5.
    Sullivan, G.J., Ohm, J.-R., Han, W.-J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1649–1668 (2012)CrossRefGoogle Scholar
  6. 6.
    Wiegand, T., Sullivan, G.J., Bjøntegaard, G., Luthra, A.: Overview of the H.264/AVC video coding standard. IEEE Trans. Circuits Syst. Video Technol. 13(7), 560–576 (2003). doi: 10.1109/TCSVT.2003.815165 CrossRefGoogle Scholar
  7. 7.
    Vanne, J., Viitanen, M., Hamalainen, T.D., Hallapuro, A.: Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1885–1898 (2012). doi: 10.1109/TCSVT.2012.2223013 CrossRefGoogle Scholar
  8. 8.
    Sampaio, F., Shafique, M., Zatt, B., Bampi, S., Henkel, J.: dSVM: Energy-efficient distributed scratchpad video memory architecture. 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, pp. 1–6 (2014). doi: 10.7873/DATE.2014.033
  9. 9.
    Wang, W., Mishra, P., Ranka, S.: Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. In: Design Automation Conference (DAC 2011), San Diego (2011)Google Scholar
  10. 10.
    Dioquino, D.A.M., Rosario, K.J.S., Supe, H.F., Zarsuela, J.V., Ballesil, A.P., Reyes, J.A.: DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. In IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009), St. Julien’s (2008)Google Scholar
  11. 11.
    Soontae, K., Vijaykrishnan, N., Kandemir, M., Sivasubramaniam, A., Irwin, M.J.: Partitioned instruction cache architecture for energy efficiency. ACM Trans. Embed. Comput. Syst. 2, 163–185 (2003)CrossRefGoogle Scholar
  12. 12.
    Malik, A., Moyer, B., Cermak, D.: A low power unified cache architecture providing power and performance flexibility. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2000), Rapallo, Italy (2000)Google Scholar
  13. 13.
    Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Kim, H.S., Ye, W.: Energy-driven integrated hardware-software optimizations using SimplePower. In: Proceedings of 27th International Symposium on Computer Architecture, Vancouver, Canada (2000)Google Scholar
  14. 14.
    Alves, M.A.Z.: Increasing Energy Efficiency of Processor Cache Via Line Usage Predictors, Porto Alegre. Federal University of Rio Grande do Sul, Rio Grande do Sul (2014)Google Scholar
  15. 15.
    Pedre, S., Krajník, T., Todorovich, E., Borenszt, P.: Accelerating embedded image processing for real time: a case study. J. Real-Time Image Process. 11(2), 349–374 (2013). doi: 10.1007/s11554-013-0353-2 CrossRefGoogle Scholar
  16. 16.
    Silveira, D., Povala, G., Amaral, L., Zatt, B., Porto, M., Agostini, L.: Efficient Reference Frame Compression Scheme for Video Coding. Springer, Berlin (2015)Google Scholar
  17. 17.
    Sinangil, M.E., Chandrakasan, A.P., Sze, V., Zhou, M.: Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine. 19th IEEE International Conference on Image Processing, Orlando, FL, pp. 1533–1536 (2012). doi: 10.1109/ICIP.2012.6467164
  18. 18.
    Bossen, F., Bross, B., Suhring, K., Flynn, D.: HEVC complexity and implementation analysis. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1685–1696 (2012)CrossRefGoogle Scholar
  19. 19.
    Vanne, J., Viitanen, M., Hamalainen, T.D., Hallapuro, A.: Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1885–1898 (2012)CrossRefGoogle Scholar
  20. 20.
    Correa, G., Assunção, P., Agostini, L., da Silva Cruz, L.A.: Performance and computational complexity assessment of high-efficiency video encoders. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1899–1909 (2012)CrossRefGoogle Scholar
  21. 21.
    Correa, G., Assuncao, P., Agostini, L., da Silva Cruz, L.A.: Complexity scalability for real-time HEVC encoders. J. Real-Time Image Process. 12(1), 107–122 (2014). doi: 10.1007/s11554-013-0392-8 CrossRefGoogle Scholar
  22. 22.
    Gonzalez, R., Horowitz, M.: Energy dissipation in general purpose microprocessors. IEEE J. Solid-State Circuits. 31(9), 1277–1284 (1996). doi: 10.1109/4.535411 CrossRefGoogle Scholar
  23. 23.
    Iranpour, V., Kuchcinski, K.: Memory architecture evaluation for video encoding on enhanced embedded processors. In: Vassiliadis, S., Wong, S., Hämäläinen, T.D. (eds.) Embedded Computer Systems: Architectures, Modeling, and Simulation: 6th International Workshop, SAMOS 2006, Samos, Greece,17–20 July 2006, pp. 309–320. Springer, Berlin, HeidelbergGoogle Scholar
  24. 24.
    Jin, L., Cho, S.: Reducing cache traffic and energy with macro data load. In: ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design, Tegernsee, pp. 147–150 (2006). doi: 10.1145/1165573.1165608
  25. 25.
    Grellert, M., Zatt, B., Shafique, M., Bampi, S., Henkel, J.: Complexity control of HEVC encoders targeting real-time constraints J. Real-Time Image Process. 12, 1–20 (2016)CrossRefGoogle Scholar
  26. 26.
    High Efficiency Video Coding (HEVC) Test Model 16.2 (HM 16.2) Encoder Description, ISO/IEC JTC1/SC29/WG11 N14970, vol. 1, Strasbourg, France, 2014Google Scholar
  27. 27.
    x265: x265 HEVC Encoder/H.265 Video Codec (2013). [Online]. Accessed 16 Nov 2016
  28. 28.
    Monteiro, E., Grellert, M., Zatt, B., Bampi, S.: Rate-distortion and energy performance of HEVC video encoders. In: PATMOS, Palma de Mallorca (2014)Google Scholar
  29. 29.
    Nethercote, N., Seward, J.: Valgrind: a framework for heavyweight dynamic binary instrumentation, San Diego (2007)Google Scholar
  30. 30.
    Silveira, D.S., Bampi, S., Moro, G.B., da Cruz, E.H.M., Navaux, P.O.A., Schnorr, L.M.: System energy analysis for shared memory multiprocessing applications. In: IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo, Monaco (2016)Google Scholar
  31. 31.
    Bjontegaard, G.: Calculation of average PSNR differences between RD-curves, Technical Report VCEG-M33, ITU-T SG16/Q6, Austin, TX, USA (2001)Google Scholar
  32. 32.
    Bossen, F.: Common test conditions and software reference configurations—JCTVC-H1100 (2012)Google Scholar
  33. 33.
    ITU-T: Subjective video quality assessment methods for multimedia applications, Geneva (1999)Google Scholar
  34. 34.
    Mativi, A.C., Monteiro, E.R., Bampi, S.: Memory access profiling for HEVC encoders. In: 7th Latin American Symposium on Circuits and Systems (LASCAS), Florianopolis (2016)Google Scholar
  35. 35.
    Kültürsay, E., Kandemir, M., Sivasubramaniam, A., Mutlu, O.: Evaluating STT-RAM as an energy-efficient main memory alternative, Los Alamitos (2013)Google Scholar
  36. 36.
    Sampio, F., Shafique, M., Zatt, B., Bampi, S., Henkel, J.: Energy-efficient architecture for advanced video memory, Piscataway (2014)Google Scholar
  37. 37.
    Naccari, M., Gabriellini, A., Mrak, M., Blasi, S.G., Zupancic, I., Izquierdo, E.: HEVC coding optimisation for ultra high definition television services. In: Picture coding symposium (PCS), Cairns, Australia (2015)Google Scholar
  38. 38.
    Options, X.P.: x265 Preset options [Online]. Accessed Nov 2016

Copyright information

© Springer-Verlag Berlin Heidelberg 2017

Authors and Affiliations

  • Eduarda Monteiro
    • 1
    Email author
  • Mateus Grellert
    • 1
  • Bruno Zatt
    • 2
  • Sergio Bampi
    • 1
  1. 1.Informatics Institute, PPGCFederal University of Rio Grande do Sul, UFRGSPorto AlegreBrazil
  2. 2.Group of Architectures and Integrated Circuits—GACIFederal University of Pelotas, UFPelPelotasBrazil

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