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IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures

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Abstract

Recent trends in the image processing field have led to the use of more heterogeneous hardware architectures. The reason for this increase is that specialized cores, compared to standard CPUs, offer a more efficient way of achieving image processing applications. Specialized cores have less power, resource, and area consumption. On the other hand, designing such a heterogenous system with specialized cores is a challenging, error-prone and time-consuming task. Therefore, new frameworks are necessary for bringing an image processing application onto a given target platform by means of a tool chain. Some frameworks exist, but they do not address each need of a heterogeneous image processing application. Common weaknesses are (1) the low utilization of the image processing domain, (2) the inflexibility of the programming paradigms for different hardware architectures. Therefore, we define our own domain-specific design language called IPOL. To automate the derivation and optimization process, a synthesis tool named Image Processing Architecture Synthesis was created. This tool will be the focus of this work.

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References

  1. Bailey, D.G.: Design for embedded image processing on FPGAs. Wiley, Singapore. ISBN 978-0470828498 (2011)

  2. Berschneider, S., Herglotz, C., Reichenbach, M., Fey, D., Kaup, A.: Estimating video decoding energies and processing times utilizing virtual hardware. In: Proceedings of 3PMCES workshop. Design, automation and test in Europe (DATE), pp. 1–2, Dresden, Germany. EDAA (2014)

  3. Chang, C., Lu, C., Yang, W.P., Chu, W.C., Yang, C., Hsiung, P.: A sysml based requirement modeling automatic transformation approach. In: 2014 IEEE 38th international computer software and applications conference workshops (COMPSACW), pp. 474–479, Vasteras, Sweden. IEE (2015)

  4. Chenini, H., Derutin, J. P., Aufrere, R., Chapuis, R.: Parallel embedded processor architecture for fpga-based image processing using parallel software skeletons. EURASIP J Adv Signal Process. 2013, 153 (2013). doi:10.1186/1687-6180-2013-153

    Article  Google Scholar 

  5. Hartmann, C., Reichenbach, M., Fey, D.: Ipol—a domain specific language for image processing applications. In: Proceedings of the international symposium on international conference on systems, pp. 40–43, Barcelona, Spain. IARIA (2015)

  6. Hegarty, J., Brunhaver, J., DeVito, Z., Ragan-Kelly, J., Cohen, N., Bell, S., Vasilyev, A., Horowitz, M., Hanrahan, P.: Darkroom: compiling high-level image processing code into hardware pipelines. Transactions on graphics (TOG)—proceedings of ACM SIGGRAPH 2014, pp. 144:1–144:11 (2014)

  7. Imperas: http://www.ovpworld.org. Accessed 31 Mar 2016

  8. Intel: http://www.intel.de/content/www/de/de/cofluent/intel-cofluent-studio.html. Accessed 31 Mar 2016

  9. Kerbyson, D. J., Atherton, T. J.: Circle detection using hough transform filters. In: Image processing and its applications, pp. 370–374, Edinburgh, Scotland. IEEE (1995)

  10. Milford, M., McAllister, J.: Valved dataflow for fpga memory hierarchy synthesis. In: Proceedings acoustics, speech and signal processing (ICASSP), pp. 1645–1648, Kyoto, Japan. IEEE (2012)

  11. Patterson, D., Hennessy, J.: Computer organization and design. Morgan Kaufmann. Oxford, UK. ISBN 978-0124077263 (2014)

  12. Reiche, O., Häublein, K., Reichenbach, M., Hannig, F., Teich, J., Fey, D.: Automatic optimization of hardware accelerators for image processing. In: Proceedings of the DATE friday workshop on heterogeneous architectures and design methods for embedded image systems (HIS), pp. 10–15. Grenoble, France (2015)

  13. Reiche, O., Häublein, K., Reichenbach, M., Hannig, F., Teich, J., Fey, D.: Automatic optimization of hardware accelerators for image processing. In: Heterogeneous architectures and design methods for embedded image systems (HIS 2015), pp. 10–15. Grenoble, France (2015)

  14. Reichenbach, M., Pfundt, B., Fey, D.: Framework for parameter analysis of fpga-based image processing architectures. In: Proceedings of international conference on systems, architectures, modeling and simulation (SAMOS), pp. 1–7, Samos, Greece. IEEE (2015)

  15. Schmidt, M., Reichenbach, M., Fey, D.: A generic vhdl template for 2d stencil code applications on fpgas. In: International symposium on object/component/service-oriented real-Time distributed computing workshops (ISORCW), pp. 180–187, Shenzen, China. IEEE (2012)

  16. Schumacher, F., Holzer, M., Greiner, T., Rosenstiel, W.: Modeling and code generation of recursive algorithms with extended uml activity diagrams. In: Radioelektronika (RADIOELEKTRONIKA), 21st international conference, pp. 1–4, Brno, Czech. IEEE (2011)

  17. Vidal, J., Lamotte, F., Gogniat, G., Soulard, P., Diguet, J.: A co-design approach for embedded system modeling and code generation with uml and marte. In: Proceedings of design, automation and test in Europe (DATE) conference and exhibition, pp. 226–231, Nice, France. EDAA (2009)

  18. Burge, M.J., Burger, W.: Principles of digital image processing: core algorithms. Springer, London, UK. ISBN 978-1848001947 (2009)

  19. Burge, M.J., Burger, W.: Principles of digital image processing: fundamental techniques. Springer, London, UK. ISBN 978-1848001947 (2011)

  20. Yoo, J., Ahn, C.: Image matching using peak signal-to-noise ratio based occlusion detection. IET Image Process. 6, 483–495 (2012). doi:10.1049/iet-ipr.2011.0025

    Article  MathSciNet  Google Scholar 

  21. Zuniga, O.A., Haralick, R.M.: Integrated directional derivative gradient operator. IEEE Trans. Syst. Man Cybern. 17, 508–517 (1987). doi:10.1109/TSMC.1987.4309068

    Article  Google Scholar 

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Acknowledgments

This work was financially supported by the Research Training Group 1773 “Heterogeneous Image Systems”, funded by the German Research Foundation (DFG).

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Correspondence to C. Hartmann.

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Hartmann, C., Häublein, K., Reichenbach, M. et al. IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. J Real-Time Image Proc 14, 549–564 (2018). https://doi.org/10.1007/s11554-016-0587-x

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