Abstract
Loop tiling (or loop blocking) is a well-known loop transformation to improve temporal locality in nested loops which perform matrix computations. When targeting caches that have low associativities, one of the key challenges for loop tiling is to simultaneously minimize capacity misses and conflict misses. This paper analyzes the effect of the tile size and the array-dimension size on capacity misses and conflict misses. The analysis supports the approach of combining tile-size selection (to minimize capacity misses) with array padding (to minimize conflict misses).
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This work is sponsored in part by National Science Foundation of USA under Grant Nos. ST-HEC-0444285, CCR-950254, ACI/ITR-0082834 and CCR-9975309, by Indiana 21st Century Fund, and by a donation from Sun Microsystems, Inc.
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Li, Z. Simultaneous Minimization of Capacity and Conflict Misses. J Comput Sci Technol 22, 497–504 (2007). https://doi.org/10.1007/s11390-007-9069-8
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DOI: https://doi.org/10.1007/s11390-007-9069-8