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Parallel Switch System with QoS Guarantee for Real-Time Traffic

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Abstract

This paper studies the load-balancing algorithm and quality of service (QoS) control mechanism in a 320Gb/s switch system, which incorporates four packet-level parallel switch planes. Eight priorities for both unicast and multicast traffic are implemented, and the highest priority with strict QoS guarantee is designed for real-time traffic. Through performance analysis under multi-priority burst traffic, we demonstrate that the load-balancing algorithm is efficient, and the switch system not only provides excellent performance to real-time traffic, but also efficiently allocates bandwidth among other traffic of lower priorities. As a result, this parallel switch system is more scalable towards next generation core routers with QoS guarantee, as well as ensures in-order delivery of IP packets.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, P.R. China

    Wen-Jie Li, Bin Liu & Yang Xu

  2. PMC-SIERRA, 8555 Baxter Place, Burnaby, BC, V5A4V7, Canada

    Heng Liao

Authors
  1. Wen-Jie Li
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  2. Bin Liu
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  3. Yang Xu
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  4. Heng Liao
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Corresponding author

Correspondence to Wen-Jie Li.

Additional information

Supported by the National Natural Science Foundation of China under Grant Nos. 60573121 and 60373007, the China/Ireland Science and Technology Collaboration Research Fund (CI-2003-02), the National Research Foundation for the Doctoral Program of Higher Education of China (Grant No. 20040003048).

Wen-Jie Li received the B.E. and Ph.D. degrees from the Dept. Computer Science and Technology, Tsinghua University, China, in 2000 and 2005, respectively. His research interests include high-speed broadband networks, core router architecture, practical scheduling algorithms and QoS.

Bin Liu received his M.S. and Ph.D. degrees both in computer science & engineering from Northwestern Polytechnical University, Xi’an, China in 1988 and 1993, respectively. From 1993 to 1995 he was a postdoctoral research fellow in the National Key Lab of SPC and Switching Technologies, Beijing University of Post and Telecommunications. In 1995 he transferred to Dept. Computer Science and Technology, Tsinghua University as an associate professor, where he mainly focused on multimedia networking including ATM switching technology and Internet infrastructure. He became a full professor of Computer Science and Technology at Tsinghua University, Beijing in 1999 and currently he is the director of the Lab of Broadband Networking Technologies in the university. His current research areas include high performance switches/routers, high speed network security, network processors and traffic engineering. He has served as the Communications & Information Technical Committee (CIS TC) member, guest editor of JSAC special issues on “High Speed Network Security” and TPC members of INFOCOM05/06, HPSR05, ICCCN05 and SUTC2006.

Yang Xu received the B.E. degree in computer science and technology from Beijing University of Posts and Telecommunications, P. R. China, in 2001. He is a Ph.D. candidate in computer science and technology at Tsinghua University. His main research interests include next-generation networks, packet switching and scheduling, design and analysis of high-performance router. He is a student member of IEEE.

Heng Liao received the Ph.D. degree from Tsinghua University, in 1996. He is currently a principal engineer with PMC-Sierra, Inc. Dr. Liao serves as the chief architect for PMC’s SAS interconnect and RAID Products. Prior to joining PMC-Sierra, Dr. Liao was a post-doctorial research associate at Princeton University, studying various parallel processor architectures and complier techniques. Dr. Liao has over 8 years of experience in the storage and communication IC industry and has worked in various design roles. Dr. Liao has over 25 US and international patents pending or awarded in the field of communication systems, switching techniques, micro-architectures, and storage systems.

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Li, WJ., Liu, B., Xu, Y. et al. Parallel Switch System with QoS Guarantee for Real-Time Traffic. J Comput Sci Technol 21, 1012–1021 (2006). https://doi.org/10.1007/s11390-006-1012-x

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  • DOI: https://doi.org/10.1007/s11390-006-1012-x

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