Journal of Computer Science and Technology

, Volume 21, Issue 1, pp 141–146 | Cite as

A Test Approach for Look-Up Table Based FPGAs

  • Ehsan AtoofianEmail author
  • Zainalabedin Navabi


This paper describes a test architecture for minimum number of test configurations in test of FPGA (Field Programmable Gate Array) LUTs (Look Up Tables). The test architecture includes a TPG (Test Pattern Generator) that is tested while it is generating test data for LEs (Logic Elements) that form the CUT (Circuit Under Test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (Output Response Analyzer) and having to perform many more reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.


FPGA testing BIST LUT testing memory testing TPG with LE 


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Copyright information

© Springer Science + Business Media, Inc. 2006

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of TehranTehranIran

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