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A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

  • Special Section on Advanced Computer Systems Architecture
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Abstract

The on-chip memory performance of embedded systems directly affects the system designers' decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory (FSRAM), is investigated for embedded systems. To realize sequential accesses, small “links” are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buffer (SAB). To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St., S.E. Minneapolis, MN, 55455, U.S.A.

    Ying Chen, David J. Lilja & Kia Bazargan

  2. Data Communications Division, Cypress Semiconductor Corp., 198 Champion Ct., San Jose, CA, 95134, U.S.A.

    Karthik Ranganathan

  3. Marvell Semiconductor, 5400 Bayfront Plaza, Mailstop E-201, Santa Clara, CA, 95054, U.S.A.

    Vasudev V. Pai

Authors
  1. Ying Chen
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  2. Karthik Ranganathan
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  3. Vasudev V. Pai
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  4. David J. Lilja
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  5. Kia Bazargan
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Corresponding author

Correspondence to Ying Chen.

Additional information

Supported in part by the Minnesota Supercomputing Institute.

Ying Chen received her Ph.D. and M.S. degrees in electrical engineering from the University of Minnesota and the B.S. degree in electrical engineering from Tsinghua University. Starting from fall of 2005, she will work as an assistant professor at San Francisco State University. Her main research interests include hardware verification methodology, multiprocessors, multithreaded architectures, memory systems, and reconfigurable computing. She is a student member of the IEEE.

Karthik Ranganathan received his Bachelors degree in electronics engineering from the University of Mumbai, India. He was an ECE Department Fellow as well as a Graduate Teaching Assistant at the University of Minnesota. He has interned with the VLSI division at Seagate Technologies and with the Applications Engineering group at Cypress Semiconductor. Subsequently, he graduated with a Master's Degree in electrical engineering from the University of Minnesota. He has been a Product/Test Engineer with the Data Communications Division at Cypress Semiconductor for about 2 years. He is currently a Sr. Product Engineer working with the “CCD” Division of Cypress Semiconductor Corp.

Vasudev V. Pai received the B.E. (Hons.) degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India and the M.S. degree in electrical engineering from the University of Minnesota, Twin Cities in 2000 and 2005, respectively. He was with IBM Corporation from 2000 to 2002 where he worked on the hardware verification of the Power4 processor at Austin, TX. He has also held internships at Texas Instruments and Cypress Semiconductor. Currently, he is working as a digital design engineer at Marvell Semiconductor, Santa Clara, CA.

David J. Lilja received the Ph.D. and M.S. degrees, both in electrical engineering, from the University of Illinois at Urbana-Champaign, and a B.S. degree in computer engineering from Iowa State University in Ames. He currently is a professor and Head of Electrical and Computer Engineering, and a Fellow of the Minnesota Supercomputing Institute, at the University of Minnesota in Minneapolis. He also serves as a member of the graduate faculties in computer science and scientific computation. He has been a visiting senior engineer in the Hardware Performance Analysis group at IBM in Rochester, Minnesota, and a visiting professor at the University of Western Australia in Perth. Previously, he worked as a research assistant at the Center for Supercomputing Research and Development at the University of Illinois, and as a development engineer at Tandem Computers Incorporated (now a division of Hewlett-Packard) in Cupertino, California. He has chaired and served on the program committees of numerous conferences; was a distinguished visitor of the IEEE Computer Society; is a member of the IEEE and the ACM; and is a registered Professional Engineer in Electrical Engineering in Minnesota and California. His primary research interests are in high-performance computer architecture, parallel computing, hardware-software interactions, nano-computing, and performance analysis.

Kia Bazargan received his Bachelors degree in computer science from Sharif University in Tehran, Iran, and his M.S. and Ph.D. degrees in electrical and computer engineering from Northwestern University in Evanston, IL in 1998 and 2000 respectively. He is currently an assistant professor in the electrical and computer engineering at the University of Minnesota. He has served on the technical program committee of a number of IEEE sponsored conferences (e.g., ISPD, ICCAD, ASP-DAC, GLSVLSI). He was a guest co-editor of ACM Transactions on Embedded Computing Systems (ACM TECS), Special Issue on Dynamically Adaptable Embedded Systems in 2003. He is an Associate Editor of IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. He was a recipient of NSF CAREER award in 2004. His research interests are computer-aided design, FPGAs and reconfigurable computing.

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Chen, Y., Ranganathan, K., Pai, V.V. et al. A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J Comput Sci Technol 20, 596–606 (2005). https://doi.org/10.1007/s11390-005-0596-x

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