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The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy

  • Special Section on Advanced Computer Systems Architecture
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Abstract

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.

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References

  1. Machanick P, Salverda P, Pompe L. Hardware-software trade-offs in a Direct Rambus implementation of the RAMpage memory hierarchy. In Proc. 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 1998, pp.105–114.

  2. Machanick P. Scalability of the RAMpage memory hierarchy. South African Computer Journal, August 2000, (25): 68–73.

  3. Machanick P. Initial experiences with dreamy memory and the RAMpage memory hierarchy. In Proc. Ninth Asia-Pacific Computer Systems Architecture Conf., Beijing, September 2004, pp.146–159.

  4. ARM. The ARM11 Microprocessor and ARM PrimeXsys Platform. ARM, October 2002. http://www.arm.com/pdfs/ARM11%20Core%20%%20Platform%20Whitepaper.pdf.

  5. Micron Technology. 256MB: ×4, ×8, ×16 DDR SDRAM, December 2003, Data Sheet. http://download.micron.com/pdf/datasheets/dram/ddr/256M×4×8×16DDR.pdf.

  6. Machanick P. The case for SRAM main memory. Computer Architecture News, December 1996, 24(5): 23–30.

    Article  Google Scholar 

  7. Wulf W A, McKee S A. Hitting the memory wall: Implications of the obvious. Computer Architecture News, March 1995, 23(1): 20–24.

    Article  Google Scholar 

  8. Johnson E E. Graffiti on the memory wall. Computer Architecture News, September 1995, 23(4): 7–8.

    Article  Google Scholar 

  9. Jochen Liedtke. Toward real microkernels. Commun. ACM, 1996, 39(9): 70–77.

    Google Scholar 

  10. Uwe Dannowski, Kevin Elphinstone, Jochen Liedtke et al. The L4Ka vision. Technical report, University of Karlsruhe, System Architecture Group, April 2001. http://i30www.ira.uka.de/research/documents/l4ka/L4Ka.pdf.

  11. Jay Lepreau, Mike Hibler, Bryan Ford et al. In-kernel servers on Mach 3.0: Implementation and performance. In USENIX MACH III Symp., USENIX Association, 1993, pp.39–56.

  12. Engler D R, Kaashoek M F, O'Toole Jr J. Exokernel: An operating system architecture for application-level resource management. In Proc. 15th ACM Symp. Operating Systems Principles, ACM Press, 1995, pp.251–266.

  13. Alessandro Maccari. Experiences in assessing product family software architecture for evolution. In Proc. 24th Int. Conf. Software Engineering, ICSE'02, ACM Press, 2002, pp.585–592.

  14. Peter Sanders. Creating Symbian OS phones. White Paper, April 2002. http://www.symbian.com/technology/create-symb-OS-phones.html.

  15. David McCullough. uCLinux for Linux programmers. Linux J., July 2004, (123).

  16. Ashley Saulsbury, Fong Pong, Andreas Nowatzyk. Missing the memory wall: The case for processor/memory integration. In Proc. 23rd Ann. Int. Symp. Computer Architecture, 1996, pp.90–101.

  17. Richard Fromm, Stylianos Perissakis, Neal Cardwell et al. The energy efficiency of IRAM architectures. In Proc. 24th Int. Symp. Computer Architecture, Denver, CO, 1997, pp.327–337.

  18. Luca Benini, Alberto Macii, Massimo Poncino. Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. ACM Trans. Embedded Computing Sys., 2003, 2(1): 5–32.

  19. Yun Cao, Hiroyuki Tomiyama, Takanori Okuma, Hiroto Yasuura. Data memory design considering effective bitwidth for low-energy embedded systems. In Proc. 15th Int. Symp. System Synthesis, Kyoto, Japan, 2002, pp.201–206.

  20. Alvin R Lebeck, Xiaobo Fan, Heng Zeng, Carla Ellis. Power aware page allocation. In Proc. 9th Int. Conf. Arch. Support for Programming Languages and Operating Systems (ASPLOS-9), Cambridge, MA, November 2000, pp.105–116.

  21. Hai Huang, Padmanabhan Pillai, Kang G Shin. Design and implementation of power-aware virtual memory. In Proc. USENIX 2003 Annual Technical Conference, San Antonio, Tx, June 2003, pp.57–70.

  22. Hojun Shim, Yongsoo Joo, Yongseok Choi et al. Low-energy off-chip SDRAM memory systems for embedded applications. ACM Trans. Embedded Computing Sys., 2003, 2(1): 98–130.

    Article  Google Scholar 

  23. Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proc. 28th Ann. Int. Symp. Computer Architecture, Gteborg, Sweden, 2001, pp.240–251.

  24. Machanick P. Correction to RAMpage ASPLOS paper. Computer Architecture News, September 1999, 27(4): 2–5.

    Article  Google Scholar 

  25. Machanick P, Patel Z. L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. In Proc. Eighth Asia-Pacific Computer Systems Architecture Conf., Aizu-Wakamatsu City, Japan, September 2003, pp.305–319.

  26. NEC. MOS integrated circuit μPD4482162, 4482182, 4482322, 4482362, Data Sheet No. M14522EJ3V0DS00, December 2002. http://www.necel.com/memory/pdfs/M14522EJ3V0DS00.pdf.

  27. ARM. ARM1136JF-S and ARM1136J-S Technical Reference Manual. ARM, revision r0p2 edition, 2003. http://www.arm.com/pdfs/DDI0211D_arm1136_r0p2_trm.pdf.

  28. Hennessy J L, Patterson D A. Computer Architecture: A Quantitative Approach 3rd Edition. Morgan Kauffmann, San Francisco, CA, 2003.

  29. Binkert N L, Hallnor E G, Reinhardt S K. Network-oriented full-system simulation using M5. In Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003, pp.36–43.

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Authors and Affiliations

  1. School of ITEE, University of Queensland, Brisbane, Qld 4072, Australia

    Philip Machanick

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  1. Philip Machanick
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Correspondence to Philip Machanick.

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Financial support for this work has been received from the University of Queensland.

Philip Machanick is a senior member of the IEEE, and a member of ACM. He is director of IT programs at the School of IT and Electrical Engineering at the University of Queensland, Australia. He has published works in memory hierarchy design, computer science education and a number of areas of computer science.

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Machanick, P. The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy. J Comput Sci Technol 20, 586–595 (2005). https://doi.org/10.1007/s11390-005-0586-z

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