Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 237–242 | Cite as

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

  • Yin-Shui XiaEmail author
  • Lun-Yao Wang
  • A. E. A. Almaini


A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.


CMOS flip-flops multiple-valued clock multiple-valued logic 


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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • Yin-Shui Xia
    • 1
    • 2
    Email author
  • Lun-Yao Wang
    • 2
  • A. E. A. Almaini
    • 1
  1. 1.School of EngineeringNapier UniversityEdinburghU.K.
  2. 2.School of Information and Engineering ScienceNingbo UniversityNingboP.R. China

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