Advertisement

Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 237–242 | Cite as

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

  • Yin-Shui XiaEmail author
  • Lun-Yao Wang
  • A. E. A. Almaini
Article

Abstract

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.

Keywords

CMOS flip-flops multiple-valued clock multiple-valued logic 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Current K W. Multiple-valued logic memory circuit. International Journal of Electronics, 1995, 78: 547–555.Google Scholar
  2. [2]
    Vranesic Z G. Multiple-valued logic: An introduction and overview. IEEE Trans. Computers, 1977, C-26: 1181–1182.Google Scholar
  3. [3]
    Current K W. Quaternary static latch circuit. International Journal of Electronics, 2001, 88: 449–452.Google Scholar
  4. [4]
    Prosser F, Wu X, Chen X. Ternary CMOS flip-flops and their applications. IEE Proceedings, 1988, 135E: 256–272.Google Scholar
  5. [5]
    Wu X, Chen X. Quaternary CMOS circuits based on transmission function theory. Science in China $($Series A$)$, 1989, (5): 528–536.Google Scholar
  6. [6]
    Wu X, Shen J, Chen X. CMOS multivalued flip-flops based on new presetting scheme and transmission function theory. In Proceedings of International Workshop on Spectral Technique, Beijing, 1994, pp.74–77.Google Scholar
  7. [7]
    Xia Y, Wu X. Design of nMOS quaternary flip-flops and their applications. Journal of Electronics, 1998, 15(4): 347–356.Google Scholar
  8. [8]
    Zhuang N, Wu H. Novel ternary JKL flip-flops. Electronics Letters, 1990, 26: 1145–1146.Google Scholar
  9. [9]
    Xia Y, Wu X. Multivalued clock pulse and mutipulse-multivalued flip-flops in parallel type. Acta Electronica Sinica, 1997, 25(8): 52–54.Google Scholar
  10. [10]
    Zukeran C et al. Design of new low-power quaternary CMOS logic circuits based on multiple ion implants. IEEE International Symposium on Multiple-Valued Logic, Kingston, 1985, pp.84–90.Google Scholar
  11. [11]
    Wu X. Theory of transmission switches and its application to design of CMOS digital circuits. International Journal of Circuit Theory and Applications, 1992, 20: 349–356.Google Scholar
  12. [12]
    Weste N, Eshraghian K. Principle of CMOS VLSI design: A Systems Perspective. Second Edition, Addison-Wesley Publishing Company, USA, 1992.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • Yin-Shui Xia
    • 1
    • 2
    Email author
  • Lun-Yao Wang
    • 2
  • A. E. A. Almaini
    • 1
  1. 1.School of EngineeringNapier UniversityEdinburghU.K.
  2. 2.School of Information and Engineering ScienceNingbo UniversityNingboP.R. China

Personalised recommendations