Abstract
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
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Supported in part by the National Natural Science Foundation of China (NSFC) under Grant No.60273093 and in part of the China-UK joint project supported by the NSFC and the Royal Society of the UK.
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Xia, YS., Wang, LY. & Almaini, A.E.A. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. J Comput Sci Technol 20, 237–242 (2005). https://doi.org/10.1007/s11390-005-0237-4
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DOI: https://doi.org/10.1007/s11390-005-0237-4