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Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 216–223 | Cite as

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead

  • Abdil Rashid MohamedEmail author
  • Zebo Peng
  • Petru Eles
Article

Abstract

This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

Keywords

BIST insertion test synthesis wiring area simulated annealing. 

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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Department of Computer and Information ScienceLinköping UniversitySweden

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