Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 216–223 | Cite as

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead

  • Abdil Rashid MohamedEmail author
  • Zebo Peng
  • Petru Eles


This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.


BIST insertion test synthesis wiring area simulated annealing. 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Chiu S S K, Papachristou C A. A built-in self-testing approach for minimizing hardware overhead. In Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors} (ICCD ‘91), Cambridge, MA, U.S.A., Oct. 14–16. 1991, pp.282–285,Google Scholar
  2. [2]
    Nicolici N, Al-Hashimi B M, Brown A D, Williams A C. BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Nov. 2000, 19(11): 1375–1385.Google Scholar
  3. [3]
    Avra L. Allocation and assignment in high-level synthesis for self-testable data paths. In Proc. the International Test Conference, Nashville, 1991, pp.463–472.Google Scholar
  4. [4]
    Alvandpour A, Svensson C. A wire capacitance estimation technique for power consuming interconnections at high levels of abstraction. In Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS97), Louvain-la-Neuve, Belgium, 1997.Google Scholar
  5. [5]
    Hallberg J, Peng Z. Estimation and consideration of interconnection delays during high level synthesis. In Proc. the 24th Euromicro Conference, Vasteras, Sweden, Aug. 1998, Vol.1, pp.349–356.Google Scholar
  6. [6]
    Goel S K, Marinissen E J. Layout-driven SoC test architecture design for test time and wire length minimization. In Proc. the Design, Automation and Test in Europe, 2003, pp.738–743.Google Scholar
  7. [7]
    Reeves C R. Modern Heuristic Techniques for Combinatorial Problems. Blackwell Scientific Publications, 1993.Google Scholar
  8. [8]
    Mohamed A R, Peng Z, Eles P. BIST synthesis: An approach to resources optimization under test time constraints. In Proc. the 5th Design and Diagnostic of Electronic Circuits and Systems (DDECS2002), Brno, Czech Republic, 2002, pp.346–351.Google Scholar
  9. [9]
    Ghosh I, Jha N K, Bhawmik S. A BIST scheme for RTL circuits based on symbolic testability analysis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2000, 19(1): 111–128.Google Scholar
  10. [10]
    Ghosh I, Jha N K, Bhawmik S. A BIST scheme for RTL controller-data paths based on symbolic testability analysis. In Proc. the 35th ACM IEEE Design Automation Conference, San Francisco, CA, U.S.A., 1998, pp.554–559.Google Scholar
  11. [11]
    Moshnyaga V G, Tumaru K. A placement driven methodology for high-level synthesis of sub-micron ASICS. In International Symposium on Circuits and Systems (ISCAS’96), May 1996, pp.572–575.Google Scholar
  12. [12]
    M Tien-Chien Lee. High-Level Test Synthesis of Digital VLSI Circuits. Artech House, 1997.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Department of Computer and Information ScienceLinköping UniversitySweden

Personalised recommendations