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Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

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Abstract

This paper presents a test resource partitioning technique based on an efficient response compaction design~called quotient compactor(q-Compactor). Because q-Compactor is a single-output compactor, high compaction ratios can be obtained even for chips with a small number of outputs. Some theorems for the design of q-Compactor are presented~to achieve full diagnostic ability, minimize error cancellation and handle unknown bits in the outputs of the circuit under test (CUT). The q-Compactor can also be moved to the load-board, so as to compact the output response of the CUT even during functional testing. Therefore, the number of tester channels required to test the chip is significantly reduced. The experimental results on the ISCAS ‘89 benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is very efficient.

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Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, P.R. China

    Yin-He Han, Xiao-Wei Li & Hua-Wei Li

  2. Graduate School of Chinese Academy of Sciences, Beijing, 100039, P.R. China

    Yin-He Han & Xiao-Wei Li

  3. Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA, 94043, U.S.A.

    Anshuman Chandra

Authors
  1. Yin-He Han
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  2. Xiao-Wei Li
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  3. Hua-Wei Li
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  4. Anshuman Chandra
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Correspondence to Yin-He Han.

Additional information

This paper is supported by the National Natural Science Foundation of China under Grants No.90207002 and No.60242001, the Sci. & Technol. Project of Beijing under Grant No.H020120120130, and~the Foundation of Institute of Computing Technology, CAS, under Grant No. 20036160. Anshuman Chandra is supported by Synopsys Corporation. This manuscript is based on the authors’ paper that appeared in Proceedings of Asian Test Symposium,Xi’an, Nov., 2003. pp.440-445.

Yin-He Han received his B. Eng. from Nanjing University of Aeronautics and Astronautics (China) in 1997. He is now a Ph.D. candidate in computer science at Institute of Computing Technology, Chinese Academy of Sciences. His research interests include VLSI/Soc design, design for testability. He is a student member of IEEE. He received Best Paper Award of Asian Test Symposium 2003, the IEEE Test Technology Technical Council.

Xiao-Wei Li received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology (China) in 1985 and 1988 respectively, and his Ph.D. degree in computer science from Institute of Computing Technology, Chinese Academy of Sciences, in 1991. Dr. Li joined Peking University as a postdoctoral research associate in 1991, and was promoted to associate professor in 1993, all with the Department of Computer Science and Technology. From 1997 to 1998, he was a visiting research fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong. In 1999 and 2000, he was a Visiting Professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. He joined Institute of Computing Technology, Chinese Academy of Sciences, as a professor in 2000. His research interests include VLSI/Soc design verification and test generation, design for testability, low-power design, dependable computing. Dr. Li received the Natural Science Award from Chinese Academy of Sciences in 1992, the Certificate of Appreciation from IEEE Computer Society in 2001. He is a senior member of IEEE. He is an area editor of the Journal of Computer Science and Technology and an associate editor-in-chief of the Journal of Computer-Aided Design & Computer Graphics (in Chinese).

Hua-Wei Li received her B.S. degree in computer science from Xiangtan University (China) in 1996, and M.S. and Ph.D. degrees from Institute of Computing Technology, Chinese Academy of Sciences, in 1999 and 2001 respectively. She is now an associate professor at the Institute of Computing Technology, Chinese Academy of Sciences. Her research interests include VLSI/SoC design verification and test generation, delay test, and dependable computing. She is a member of IEEE.

Anshuman Chandra received his B.Eng. degree in electrical engineering from the University of Roorkee, Roorkee, India, and his M.S. and Ph.D. degrees in electrical and computer engineering from Duke University respectively. Now he is a senior DFT consultant of Synopsis, Inc., Mountain View, CA. His research interests include VLSI design, digital testing, and computer architecture. Mr. Chandra is a member of the ACM SIGDA. He received the Test Technology Technical Council James Beausang Student Paper Award for a paper in Proc. 2000 IEEE VLSI Test Symposium and Best Paper Award at DATE 2001.

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Han, YH., Li, XW., Li, HW. et al. Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J Comput Sci Technol 20, 201–209 (2005). https://doi.org/10.1007/s11390-005-0201-3

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  • DOI: https://doi.org/10.1007/s11390-005-0201-3

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