Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 201–209 | Cite as

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

  • Yin-He HanEmail author
  • Xiao-Wei Li
  • Hua-Wei Li
  • Anshuman Chandra


This paper presents a test resource partitioning technique based on an efficient response compaction design~called quotient compactor(q-Compactor). Because q-Compactor is a single-output compactor, high compaction ratios can be obtained even for chips with a small number of outputs. Some theorems for the design of q-Compactor are presented~to achieve full diagnostic ability, minimize error cancellation and handle unknown bits in the outputs of the circuit under test (CUT). The q-Compactor can also be moved to the load-board, so as to compact the output response of the CUT even during functional testing. Therefore, the number of tester channels required to test the chip is significantly reduced. The experimental results on the ISCAS ‘89 benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is very efficient.


System-on-a-Chip (SoC) test resource partitioning (TRP) response compaction diagnose error cancellation 


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  1. [1]
    Mitra S, Kim K S. X-compact: An efficient response compaction technique for test cost reduction. In Proc. International Test Conference, Baltimore, USA, 2002, pp.311–320.Google Scholar
  2. [2]
    Chandra A, Chakrabarty K. Test resource partitioning for SoCs. IEEE Design & Test of Computers, 2001, 18(9): 80–91.Google Scholar
  3. [3]
    Reda S, Orailoglu A. Reducing test application time through test data mutation encoding. In Proc. Design of Automation and Test in Europe (DATE), Paris, France, 2002, pp.387–393.Google Scholar
  4. [4]
    Volkerink E H, Khoche A, Mitra S. Packet-based input test data compression techniques. In Proc. Int. Test Conference, Baltimore, USA, 2002, pp.154–163.Google Scholar
  5. [5]
    Nourani M, Chin J. Testing high-speed SoCs using low-speed ATEs. In Proc. VLSI Test Symposium, Monterey, USA, 2002, pp.133–138.Google Scholar
  6. [6]
    Saluja K K, Karpovsky M. Testing computer hardware through data compression in space and time. In Proc. Int. Test Conference, Philadelphia, USA, 1983, pp.83–88.Google Scholar
  7. [7]
    Bhattacharya B B, Dmitriev A, Goessel M, Chakrabarty K. Synthesis of single-output space compactor for scan-based sequential circuits. IEEE Trans. CAD & CS, 2002, 21(10): 1171–1179.Google Scholar
  8. [8]
    Chakrabarty K, Murray B T, Hayes J P. Optimal zero-aliasing space compaction of test response. IEEE Trans. Computers, 1998, 47(11): 1171–1187.Google Scholar
  9. [9]
    Li Y K, Robinson J P. Space compression methods with output data modification. IEEE Trans. CAD & CS, 2002, 1998, 6(3): 290–294.Google Scholar
  10. [10]
    Ivanov A, Tsuji B, Zorian Y. Programmable space compactors for BIST. IEEE Trans. Computers, 1996, 45(12): 1393–1405.Google Scholar
  11. [11]
    Barnhart C, Brunkhorst V, Distler F, et al. Extending OPMISR beyond 10× scan test efficiency. IEEE Design & Test of Computers, 2002, 19(5): 65–73.Google Scholar
  12. [12]
    Wohl P, Waicukauski J A, Williams T W. Design of compactors for signature-analyzers in Built-In Self-Test. In Proc. Int. Test Conference, Baltimore, USA, 2001, pp.54–63.Google Scholar
  13. [13]
    Rajski J, Tyszer J, Wang C, Reddy S M. Convolutional compaction of test response. In Proc. Int. Test Conference, Charlotte, USA, 2003, pp.745–754Google Scholar
  14. [14]
    Wohl P, Waicukauski J A, Patel S, Maston G. Effective diagnostics through interval unloads in a BIST environment. In Proc. Design Automation Conference, New Orleans, USA, 2002, pp.249–254.Google Scholar
  15. [15]
    Brualdi R A. Introductory Combinatorics. Third Edition. Pearson Education, Inc., 1999.Google Scholar
  16. [16]
    Bardell P H, McAnney W H, Savir J. Built-In Test for VLSI: Pseudorandom Techniques. John Wiley & Sons, 1987.Google Scholar
  17. [17]
    Pomerantz I, Kundu S, Reddy S M. On output response compression in the presence of unknown output values. In Proc. Design Automation Conference, New Orleans, USA, 2002, pp.255–258.Google Scholar
  18. [18]
    Cullen C G. Algebra with Applications. Addison-Wesley, ISBN-0-673-99386-8, 1997.Google Scholar
  19. [19]
    Hamzaoglu I, Patel J H. Test set compaction algorithms for combinational circuits. In Proc. Int. Test Conference, Washington, USA, 1998, pp.283–289.Google Scholar
  20. [20]
    Lee H K, Ha D S. On the generation of test patterns for combinational circuits. Tech. Report No.12-93, Department of Electrical Engineering, Virginia Tech.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • Yin-He Han
    • 1
    • 2
    Email author
  • Xiao-Wei Li
    • 1
    • 2
  • Hua-Wei Li
    • 1
  • Anshuman Chandra
    • 3
  1. 1.Institute of Computing TechnologyChinese Academy of SciencesBeijingP.R. China
  2. 2.Graduate School of Chinese Academy of SciencesBeijingP.R. China
  3. 3.Synopsys, Inc.Mountain ViewU.S.A.

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