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Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 195–200 | Cite as

Delay Testing Viability of Gate Oxide Short Defects

  • J. M. GallièreEmail author
  • M. Renovell
  • F. Azaïs
  • Y. Bertrand
Article

Abstract

Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and I DDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location. It is demonstrated that i) GOS has a significant impact on gate delay, ii) GOS located close to the source of the transistor and with small resistance has very high impact.

Keywords

VLSI delay testing defect gate oxide short (GOS) 

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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • J. M. Gallière
    • 1
    Email author
  • M. Renovell
    • 1
  • F. Azaïs
    • 1
  • Y. Bertrand
    • 1
  1. 1.Laboratoire d’Informatique Robotique Microélectronique de Montpellier LIRMM-UMIIUniversité de Montpellier II: Sciences et Techniques du LanguedocMontpellier Cedex 5France

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