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Delay Testing Viability of Gate Oxide Short Defects

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Abstract

Gate Oxide Short (GOS) defects are becoming predominant as technology is scaling down. Boolean and I DDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location. It is demonstrated that i) GOS has a significant impact on gate delay, ii) GOS located close to the source of the transistor and with small resistance has very high impact.

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Authors and Affiliations

  1. Laboratoire d’Informatique Robotique Microélectronique de Montpellier LIRMM-UMII, Université de Montpellier II: Sciences et Techniques du Languedoc, UMR C5506 CNRS-161, rue Ada, 34392, Montpellier Cedex 5, France

    J. M. Gallière, M. Renovell, F. Azaïs & Y. Bertrand

Authors
  1. J. M. Gallière
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  2. M. Renovell
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  3. F. Azaïs
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  4. Y. Bertrand
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Correspondence to J. M. Gallière.

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Jean-Marc Gallière is an electronic teacher at the Electrical Engineering School of the University of Montpellier. He received the M.S. and Ph.D. degrees in electrical engineering both from the University of Montpellier, France. He is currently a postdoctoral researcher at the Microelectronic Department of the Laboratory of Computer Science, Automation and Microelectronics of Montpellier (LIRMM). His main research interests concern fault modeling.

Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: fault modeling, analog testing and FPGA testing. He is vice-chair of the IEEE TTTC (Test Technology Technical Committee) and chair of the FPGA Technical Activity Committee. He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been general chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.

Florence Azaïs received M.Eng., and Ph.D. degrees in electrical engineering from the University of Montpellier, France in 1993 and 1996, respectively. She is currently working in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of integrated circuit testing, and in particular in fault modeling and mixed-signal circuit testing. She has authored or co-authored more than 60 publications in journals or international conferences.

Yves Bertrand is a professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratory of Computer Science, Automation and Microelectronics of Montpellier (LIRMM). Previously, Yves BERTRAND worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in 1988. His main research interests are low-cost BIST architecture, fault modeling, design-for-test and built-in self-test for digital and mixed-signal integrated circuits, and design & test of microsystems. He is author or co-author of more than 150 papers in the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (National Test Resource Center).

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Gallière, J.M., Renovell, M., Azaïs, F. et al. Delay Testing Viability of Gate Oxide Short Defects. J Comput Sci Technol 20, 195–200 (2005). https://doi.org/10.1007/s11390-005-0195-x

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  • DOI: https://doi.org/10.1007/s11390-005-0195-x

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