Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 166–174 | Cite as

Efficient RT-Level Fault Diagnosis

  • Ozgur SinanogluEmail author
  • Alex Orailoglu


Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. In this paper, we propose an RT-level diagnosis methodology capable of responding to these challenges. In the proposed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnostic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and significant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches.


fault diagnosis RT-level diagnosis fault dictionary fault simulation dictionary compaction fault bit location tracing 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Boppana V, Fuchs W K. Fault dictionary compaction by output sequence removal. In IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 6–10, 1994, pp.576–579.Google Scholar
  2. [2]
    Boppana V, Hartanto I, Fuchs W K. Full fault dictionary storage based on labeled tree encoding. In VTS, 1996, pp.174–179.Google Scholar
  3. [3]
    Chess B, Larrabee T. Creating small fault dictionaries. TCAD, March 1999, 18(3): 346–356.Google Scholar
  4. [4]
    Lavo D B, Larrabee T. Making cause-effect cost effective: Low-resolution fault dictionaries. In Proc. Int. Test Conference, Oct. 30–Nov. 1, 2001, pp.278–286.Google Scholar
  5. [5]
    Pomeranz I, Reddy S M. On the generation of small dictionaries for fault location. In ICCAD, 1992, pp.272–279.Google Scholar
  6. [6]
    Ryan P G, Fuchs W K, Pomeranz I. Fault dictionary compression and equivalence class computation for sequential circuits. In ICCAD, 1993, pp.508–511.Google Scholar
  7. [7]
    Lee J, Patel J H. An architectural level test generator for a hierarchical design environment. In FTCS, 1991, pp.44–51.Google Scholar
  8. [8]
    Sinanoglu O, Orailoglu A. RT-level fault simulation based on symbolic propagation. In VTS, 2001, pp.240–245.Google Scholar
  9. [9]
    Lee J, Rudnick E M, Patel J H. Architectural-level fault simulation using symbolic data. In European Conference on Design Automation, 1993, pp.437–442.Google Scholar
  10. [10]
    Hayes J P. Computer Architecture and Organization. McGraw-Hill Inc., 1998.Google Scholar
  11. [11]
    Ashenden P. The Designer’s Guide to VHDL. Morgan-Kaufmann Publishers Inc., 1996.Google Scholar
  12. [12]
    Makris Y, Bayraktaroglu I, Orailoglu A. Invariance-based on-line test for RTL controller-datapath circuits. In VTS, 2000, pp.459–464.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Computer Science and Engineering DepartmentUniversity of CaliforniaSan Diego, La JollaU.S.A.

Personalised recommendations