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Journal of Computer Science and Technology

, Volume 20, Issue 2, pp 147–165 | Cite as

Design and Verification of High-Speed VLSI Physical Design

  • Dian ZhouEmail author
  • Rui-Ming Li
Article

Abstract

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.

Keywords

VLSI physical design floorplanning and placement interconnect delay wire sizing buffer insertion power order reduction power grid parameter extraction clock distribution 

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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Department of Electrical EngineeringThe University of Texas at DallasRichardsonU.S.A.
  2. 2.School of MicroelectronicsFudan UniversityShanghaiP.R. China

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