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Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer

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Abstract

Several research works have been undergone in the 3D IC floor planning concepts due to its higher demand and technological improvement. Floor planning is a complex step when there is a more number of a component on each layer of IC. Even though several researches have been done in this area, the optimization process is still not satisfied with the use of traditional mechanisms. Consequently, there is a need for effective optimization procedure in IC design. Hence, in this proposed work, hybrid multi verse optimizer floor planning is utilized where the node coordinates and dimensions are adjusted to attain the optimized floor planning with minimal wire length and area using best universes.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Kalasalingam Academy of Research and Higher Education, Anand Nagar, Krishnankoil, 626126, Tamilnadu, India

    Sivakumar Pothiraj

  2. Electronics and Communication Engineering, Kalasalingam Academy of Research and Higher Education, Anand Nagar, Krishnankoil, 626126, Tamilnadu, India

    Jeya Prakash Kadambarajan

  3. ECE Kalasalingam Academy of research and Higher Education, Anand Nagar, Krishnankoil, 626126, Tamilnadu, India

    Pandiaraj Kadarkarai

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  1. Sivakumar Pothiraj
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  2. Jeya Prakash Kadambarajan
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  3. Pandiaraj Kadarkarai
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Correspondence to Sivakumar Pothiraj.

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Pothiraj, S., Kadambarajan, J. & Kadarkarai, P. Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer. Wireless Pers Commun 118, 3007–3023 (2021). https://doi.org/10.1007/s11277-021-08166-z

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