Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture

Abstract

With the advancement in technology scaling and featuring new device design is being explored to meet the demand for low power and high-speed circuit design. Tri-gate junction-less FET (TGJLFET) is taken as a reference model in this study. The structure of the reference model is modified to arrive at three different device structures; the first one with two dielectric materials for gate oxide, the second one with three dielectric materials, and the third with three dielectric materials with Rectangular Core–shell (RCS) Architecture having opposite doping at the center of the channel. The performance of these three new structures was evaluated and compared with one another and also with the reference model structure. Investigated performance parameters include leakage current, sub-threshold swing, Drain induced barrier lowering (DIBL), threshold voltage, transconductance (Gm), Output Conductance (Gd), Early Voltage (Ve), Intrinsic Gain (Av), the potential at core and surface fin of the Tri-gate device. The simulation results reveal that the device with gate trioxide with RCS Architecture shows good performance with respect to the above parameters when compared with the two new device structures and reference model. Further, an inverter is simulated using TGJLFET trioxide with RCS Architecture and its DC analysis and signal to noise margin were studied. For all the simulations 3D visual TCAD device simulator from Cogenda Pvt Ltd is used.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

References

  1. 1.

    Kavalieros, J., Doyle, B., Datta, S., Dewey, G., Doczy, M., & Jin, B, et al. (2006). Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering. VLSI Technol Symp 2006.

  2. 2.

    Park, J.-T., Colinge, J.-P., & Diaz, C. H. (2001). Pi-gate SOI MOSFET. IEEE Electron Device Letter, 22 (8)

  3. 3.

    Von Arnim, K., et al. (2007). A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay large-scale integrated high performance digital circuits and SRAM. In: VLSI Technol Symp

  4. 4.

    Colinge, J.-P. (2008). FinFETs and Other Multi-Gate Transistors. New York: Springer.

    Book  Google Scholar 

  5. 5.

    Lee, C.-W., Afzalian, A., Akhavan, N. D., Yan, R., Ferain, I., & Colinge, J.-P. (2009). Junction-less multigate field-effect transistor. Applied Physics Letter 94(5), 053511–1053511-2

  6. 6.

    Lee, C.-W., et al. (2010). Performance estimation of junction-less multigate transistors. Solid-State Electron., 54(2), 97103.

    Article  Google Scholar 

  7. 7.

    Nagumo, T., & Hiramoto, T. (2006). Design guideline of multi-gate MOSFETs with substrate-bias control. IEEE Transactions on Electron Devices, 53(12), 30253031.

    Article  Google Scholar 

  8. 8.

    Gola, D., Singh, B., Singh, J., Jit, S., & Tiwari, P. K. (2019). Static and quasi-static drain current modeling of tri-gate junction-less transistor with substrate bias-induced effects, IEEE Transactions on Electron Devices, Vol. 66, No. 7,

  9. 9.

    Collaert, N., et al. (2008). Multi-gate devices for the 32 nm technology node and beyond. Solid-State Electron, 52(9), 12911296.

    Article  Google Scholar 

  10. 10.

    Roberston, J. (2004). High dielectric constant oxides. The European Physical Journal Applied Physics, 28, 265–291.

    Article  Google Scholar 

  11. 11.

    Jurczak, M., et al. (2001). Dielectric pockets-a new concept of the junctions for Deca-Nanometric CMOS devices. IEEE Transactions on Electron Devices, 48(8), 17701774.

    Article  Google Scholar 

  12. 12.

    Genius 3-D Device Simulator. (2019). Version 1.9.3-18, Reference Manual, Cogenda Pvt. Ltd., Singapore.

  13. 13.

    International Technology Roadmap for Semiconductors, https://en.wikipedia.org/wiki, 2019.

  14. 14.

    Ferain, I., Colinge, C. A., & Colinge, J.-P. (2011). Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature, 479(7373), 310–316.

    Article  Google Scholar 

  15. 15.

    Bhattacharya, D., & Jha, N. K. (2014). Finfets: from devices to architectures. Adv. Electron., 2014, 1–21.

    Article  Google Scholar 

  16. 16.

    Samares, K.(Ed.) (2013). High permittivity gate dielectric materials, springer series in advanced microelectronics, Vol. 43, https://doi.org/10.1007/978-3-642-36535-5

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to M. Prasad.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Prasad, M., Mahadevaswamy, U.B. Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture. Wireless Pers Commun 118, 619–630 (2021). https://doi.org/10.1007/s11277-020-08035-1

Download citation

Keywords

  • Tri-gate
  • Hetero-oxide
  • Trioxide
  • RCS Architec- ture
  • Junction-less
  • Potential
  • DIBL
  • N-type
  • P-type and Tri-gate with RCS architecture inverter