P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Abstract

The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the overall performance of CMPs and MPSoCs significantly. We propose P-NoC: an FPGA-based parameterized framework for analyzing the performance of NoC architectures based on various design decision parameters in this paper. The mesh and a multi-local port mesh (ML-mesh) topologies have been considered for the study. By fine-tuning various NoC parameters and synthesizing on the FPGA, identify that the performance of NoC architectures are influenced by the configuration of router parameters and the interconnect. Experiments show that the flit width, buffer depth, virtual channels parameters have a significant impact on the FPGA resources. We analyze the performance of the NoCs on six traffic patterns viz., uniform, bit shuffle, random permutation, transpose, bit complement and nearest neighbor. Configuring the router and the interconnect parameters, the ML-mesh topology yields 75% lesser utilization of FPGA resources compared to the mesh. The ML-mesh topology shows an improvement of 33.2% in network latency under localized traffic pattern. The mesh and ML-mesh topologies have 0.53\(\times\) and 0.1\(\times\) higher saturation throughput under nearest neighbor traffic compared to uniform random traffic.

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References

  1. 1.

    Pande, P. P., Grecu, C., Jones, M., Ivanov, A., & Saleh, R. A. (2005). Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Transactions on Computers, 54(8), 1025–1040.

    Article  Google Scholar 

  2. 2.

    Bell, S., Edwards, B., Amann, J., Conlin, R., Joyce, K., Leung, V., et al. (2008). TILE64-processor: A 64-core SoC with mesh interconnect. In 2008 IEEE international solid-state circuits conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3–7, 2008, pp. 88–89.

  3. 3.

    Dally, W. J., & Towles, B. (2001). Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th design automation conference, DAC 2001, Las Vegas, NV, USA, June 18–22, 2001, pp. 684–689.

  4. 4.

    Kumar, S., Jantsch, A., Millberg, M., Öberg, J., Soininen, J., Forsell, M., et al. (2002). A network on chip architecture and design methodology. In2002 IEEE computer society annual symposium on VLSI (ISVLSI 2002), 25–26 April 2002 (pp. 117–124). PA, USA: Pittsburgh.

  5. 5.

    Papamichael, M., & Hoe, J. C. (2012). CONNECT: Re-examining conventional wisdom for designing NoCs in the context of FPGAS. In Proceedings of the ACM/SIGDA 20th international symposium on field programmable gate arrays, FPGA 2012, Monterey, California, USA, February 22–24, 2012, pp. 37–46.

  6. 6.

    Wang, D., Lo, C., Vasiljevic, J., Jerger, N. D. E., & Steffan, J. G. (2014). DART: A programmable architecture for NoC simulation on fpgas. IEEE Transactions on Computers, 63(3), 664–678.

    MathSciNet  Article  Google Scholar 

  7. 7.

    Prabhu, P., Parane, K., & Talawar, B. (2018). Yanoc: Yet another network-on-chip simulation acceleration engine using FPGAs. In 31st international conference on VLSI design and 17th international conference on embedded systems, VLSID, Pune, India, January 6–10, pp. 67–72.

  8. 8.

    Micheli, G. D., & Benini, L. (2002). Networks on chip: A new paradigm for systems on chip design. In 2002 design, automation and test in Europe conference and exposition (DATE 2002), 4–8 March 2002

  9. 9.

    Owens, J. D., Dally, W. J., Ho, R., Jayasimha, D. N., Keckler, S. W., & Peh, L. (2007). Research challenges for on-chip interconnection networks. IEEE Micro, 27(5), 96–108.

    Article  Google Scholar 

  10. 10.

    Duato, J., Yalamanchili, S., & Ni, L. M. (1997). Interconnection networks—An engineering approach. Piscataway, NJ: IEEE.

  11. 11.

    Wolkotte, P. T., Hölzenspies, P. K. F., & Smit, G. J. M. (2007) Fast, accurate and detailed NoC simulations. In First international symposium on networks-on-chips, NOCS 2007, 7–9 May 2007, Princeton, NJ, USA, Proceedings, pp. 323–332.

  12. 12.

    Ju, X., & Yang, L. (2012). Performance analysis and comparison of \(2\times 4\) network on chip topology. Microprocessors and Microsystems: Embedded Hardware Design, 36(6), 505–509.

    Article  Google Scholar 

  13. 13.

    Kundu, S., & Chattopadhyay, S. J. S. (2012). Design and evaluation of mesh-of-tree based network-on-chip using virtual channel router. Microprocessors and Microsystems: Embedded Hardware Design, 36(6), 471–488.

    Article  Google Scholar 

  14. 14.

    Bergmann, N. W., Diessel, O., & Shannon, L. (2009). The effect of node size, heterogeneity, and network size on fpga based NoCs. In Proceedings of the 2009 international conference on field-programmable technology, FPT 2009, Sydney, Australia, December 9–11, 2009, IEEE Computer Society.

  15. 15.

    Loucif, S. (2015). Concentration and its impact on mesh and torus-based NoC performance. In 23rd Euromicro international conference on parallel, distributed, and network-based processing, PDP 2015, Turku, Finland, March 4–6, 2015, pp. 361–364.

  16. 16.

    Das, T. S., & Ghosal, P. (2017). Msm: Performance enhancing area and congestion aware network-on-chip architecture. In IEEE international symposium on nanoelectronic and information systems, 18–20 December 2017, Bhopal, India.

  17. 17.

    Mello, A., Tedesco, L., Calazans, N., & Moraes, F. (2005). Virtual channels in networks on chip: Implementation and evaluation on hermes NoC. In Proceedings of the 18th annual symposium on integrated circuits and systems design, SBCCI 2005, Florianolpolis, Brazil, September 4–7, 2005, pp. 178–183.

  18. 18.

    Abba, J. L. S. (2013) Examining the performance impact of NoC parameters for scalable and adaptive FPGA-based network-on-chips. In IEEE fifth international conference on computational intelligence, modelling and simulation (CIMSim), pp. 364–372.

  19. 19.

    Kamali, H. M., & Hessabi, S. (2016). Adapnoc: A fast and flexible FPGA-based NoC simulator. In 26th international conference on field programmable logic and applications, FPL 2016, Lausanne, Switzerland, August 29–September 2, 2016, pp. 1–8.

  20. 20.

    Pellauer, M., Adler, M., Kinsy, M. A., Parashar, A., & Emer, J. S. (2011). Hasim: Fpga-based high-detail multicore simulation using time-division multiplexing. In 17th International conference on high-performance computer architecture (HPCA-17 2011), February 12–16 2011, San Antonio, Texas, USA, pp. 406–417.

  21. 21.

    Guilherme Heck, F., Guazzelli, Ricardo, & Soares, R. (2012). Hardnoc: A platform to validate networks on chip through FPGA prototyping. In VIII Southern conference on programmable logic (pp. 1–6).

  22. 22.

    Naruko, T., & Hiraki, K. (2014). FOLCS: A lightweight implementation of a cycle-accurate NoC simulator on FPGAs. In Proceedings of the 3rd international workshop on many-core embedded systems (MES’2015) held on June 13, 2015 in conjunction with the 42nd international symposium on computer architecture (ISCA’2015), Portland, OR, USA, pp. 25–32.

  23. 23.

    Tedesco, L., Mello, A., Garibotti, D., Calazans, N., & Moraes, F. (2005). Traffic generation and performance evaluation for mesh-based NoCs. In Proceedings of the 18th annual symposium on integrated circuits and systems design, SBCCI 2005, Florianolpolis, Brazil, September 4–7, 2005, pp. 184–189.

  24. 24.

    Kreutz, M. E., Marcon, C. A. M., Carro, L., Wagner, F. R., & Susin, A. A. (2005). Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. In Proceedings of the 18th annual symposium on integrated circuits and systems design, SBCCI 2005, Florianolpolis, Brazil, September 4–7, 2005, pp. 190–195.

  25. 25.

    Genko, N., Atienza, D., Micheli, G. D., Mendias, J. M., Hermida, R., & Catthoor, F. (2005). A complete network-on-chip emulation framework. In 2005 design, automation and test in Europe conference and exposition (DATE 2005), 7–11 March 2005, Munich, Germany, pp. 246–251.

  26. 26.

    Abba, S., & Lee, J.-A. (2014). A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip. Microprocessors and Microsystems: Embedded Hardware Design, 38(5), 375–398.

    Article  Google Scholar 

  27. 27.

    Murawski, M., Priya, R. M. J., & Khalid, M. (2015). Design and evaluation of avalon compatible adapter and parameterizable NoC router for FPGAs. In IEEE 28th Canadian conference on electrical and computer engineering, CCECE 2015, Halifax, NS, Canada, May 3–6, 2015, pp. 553–558.

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Acknowledgements

This work was supported by the Ministry of Electronics and Information Technology, Government of India.

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Correspondence to Khyamling Parane.

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Khyamling Parane and B. M. Prabhu Prasad contributed equally to this research work.

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Parane, K., Prabhu Prasad, B.M. & Talawar, B. P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. Wireless Pers Commun (2020). https://doi.org/10.1007/s11277-020-07529-2

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Keywords

  • FPGA
  • Performance
  • Network-on-chip
  • NOCs
  • Mesh topology
  • System-on-chip