3D Multilayer Mesh NoC Communication and FPGA Synthesis

  • Adesh Kumar
  • Gaurav Verma
  • Mukul Kumar Gupta
  • Mohammad Salauddin
  • B. Khaleelu Rehman
  • Deepak Kumar


Network on chip (NoC) is the latest approach in which multiprocessors are integrated in a single chip and FPGA implementation makes it scalable and reconfigurable. It is the feasible solution for pipelined architecture and parallel processing in multiprocessor system on chip. The research article presents the NoC architecture for flexible and scalable design under 3D mesh topological structure. The design is considered for 8 layers as multilayered architecture. In one layer 64 nodes can communicate with each other. The design is developed with the help of VHDL programming in Xilinx ISE 14.2 software and functionally simulated in Modelsim 10.0 student edition software. The performance of the design is analyzed with hardware parameters and timing utilization parameters on Virtex 5 FPGA. The inter and intra communication among the nodes is verified on the same FPGA. The design is verified on Virtex-5 FPGA with 8, 16, 32, 64 and 128 bit data transfer among nodes when the NoC is fully connected and utilized. The paper also presents the comparative study of the 3D, 8 layer mesh NoC for different cluster size (2 × 2 × 2), (3 × 3 × 3) and (4 × 4 × 4), based on the FPGA synthesis parameters. The scalable architecture is applicable for the nodes communication in a wireless sensor network in which multiple nodes are communicating in defined field and configured in specific topology such as Zigbee standard (IEEE 802.15.4) follow mesh, one of the topology.


Network on chip (NoC) Multiprocessor system on chip (MPSoC) 3D mesh topology Inter communication 



Network on chip


System on chip


Multiprocessor system on chip


Field programmable gate array


Integrated system environment


Very large scale of integration


Through silicon vias


Intellectual property


Integrated circuit


Complementary metal oxide semiconductor


Very high speed integrated circuit hardware description language


Random access memory


First input first output


Register transfer level


Look up table



Authors acknowledge the department of Department of Electronics, and Instrumentation Engineering, School of Engineering, University of Petroleum and Energy Studies, Dehradun, 248007, India, for the valuable support to carry the research work.

Compliance with Ethical Standards

Conflict of interest

The authors declare that they have no conflict of interests.


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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Instrumentation Engineering, School of EngineeringUniversity of Petroleum and Energy StudiesDehradunIndia
  2. 2.Department of Electronics and Communication EngineeringJaypee Institute of Information Technology, (JIIT)NoidaIndia

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