Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks

Article
  • 23 Downloads

Abstract

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.

Keywords

Reversible logic Security Cryptography AES algorithm Toffoli gates Low power Wireless sensor networks Power analysis attacks 

References

  1. 1.
    Merkle, R. C. (1993). Two types of mechanical reversible logic. Nanotechnology, 4(2), 114–131.CrossRefGoogle Scholar
  2. 2.
    Younism, S. G., & Knight, T. F. (1994). Asymptotically zero energy split-level charge recovery logic. In Proceedings of international workshop on low power design (pp. 177–182).Google Scholar
  3. 3.
    Landauer, R. (1961). Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 5(3), 183–191.MathSciNetCrossRefMATHGoogle Scholar
  4. 4.
    Bennett, C. (1973). Logical reversibility of computation. IBM Journal of Research and Development, 17(6), 525–532.MathSciNetCrossRefMATHGoogle Scholar
  5. 5.
    Schneier, B. (1996). Applied cryptography. New York: Wiley.MATHGoogle Scholar
  6. 6.
    National Institute of Standard and Technology (NIST). (2001). Advanced Encryption Standard (AES), FIPS-197.Google Scholar
  7. 7.
    Chodowiec, P., & Gaj, K. (2003). Very compact FPGA implementation of the AES algorithm. In Proceedings of cryptographic hardware and embedded systems (pp. 319–333).Google Scholar
  8. 8.
    Chih-Pin, S., et al. (2003). A high-throughput low-cost AES processor. IEEE Communications Magazine, 41(12), 86–91.CrossRefGoogle Scholar
  9. 9.
    Saravanan, P., & Kalpana, P. (2013). A novel and systematic approach to implement reversible gates in quantum dot cellular automata. WSEAS Transactions on Circuits and Systems, 12(10), 307–316.Google Scholar
  10. 10.
    Saravanan, P., & Kalpana, P. (2014). Energy efficient reversible building blocks resistant to power analysis attacks. Journal of Circuits, Systems and Computers, 23(9), 1450127-1–1450127-40.CrossRefGoogle Scholar
  11. 11.
    Thapliyal, H., & Zwolinski, M. (2006). Reversible logic to cryptographic hardware: A new paradigm. In 49th IEEE international midwest symposium on circuits and systems (Vol. 1).Google Scholar
  12. 12.
    Nayeem, N. M., Jamal, L., & Babu, H. M. H. (2009). Efficient reversible montgomery multiplier and its application to hardware cryptography. Journal of Computer Science, 5(1), 49–56.CrossRefGoogle Scholar
  13. 13.
    Datta, K., Shrivastav, V., Sengupta, I., & Rahaman, H. (2013). Reversible logic implementation of AES algorithm. In Proceedings of 8th international conference on design & technology of integrated systems in nanoscale era (pp. 140–144).Google Scholar
  14. 14.
    Saravanan, P., & Kalpana, P. (2015). Design of SubBytes and InvSubBytes transformations of AES algorithm using power analysis attack resistant reversible logic gates. Australian Journal of Basic and Applied Sciences, 9(1), 8–18.Google Scholar
  15. 15.
    Saravanan, P., & Kalpana, P. (2015). Performance analysis of reversible finite field arithmetic architectures over GF(p) and GF(2m) in elliptic curve cryptography. Journal of Circuits, Systems and Computers, 24(8), 1550122–1550150.CrossRefGoogle Scholar
  16. 16.
    Robert, W. (2011). An introduction to reversible circuit design. In Saudi international electronics, communications and photonics conference.Google Scholar
  17. 17.
    Rudra, A., Dubey, P. K., Jutla, C. S., Vijay Kumar, Rao, J. R., & Rohatgi, P. (2001). Efficient Rijndael encryption implementation with composite field arithmetic. In Proceedings of 3rd international workshop on cryptographic hardware and embedded systems (pp. 175–188).Google Scholar
  18. 18.
    Zhang, X., & Parhi, K. K. (2004). High-speed VLSI architectures for the AES algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(9), 957–967.CrossRefGoogle Scholar
  19. 19.
    Mui, E. (2007). Practical implementation of Rijndael S-Box using Combinational logic. <http://www.xess.com/static/media/projects/Rijndael_SBox.pdf>.
  20. 20.
    Fischer, V., Drutarovsky, M., Chodowiec, P., & Gramain, F. (2005). InvMixColumn decomposition and multilevel resource sharing in AES implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(8), 989–992.CrossRefGoogle Scholar
  21. 21.
    Hua, L., & Friggstad, Z. (2005). An efficient architecture for the AES mix columns operation. IEEE International Symposium on Circuits and Systems, 5, 4637–4640.Google Scholar
  22. 22.
    Nalini, C., Anandmohan, P. V., Poornaiah, D. V. (2010). Mix/InvMixColumn decomposition and resource sharing in AES. In International conference on industrial and information systems (pp. 166–171).Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringPSG College of TechnologyPeelamedu, CoimbatoreIndia

Personalised recommendations