Augmented Recurrence Hopping Based Run-Length Coding for Test Data Compression Applications



The advancement in technologies has been increasing with increase in integrating scales which allows fabricating millions of transistors on a chip. This demands the efficient testing circuit to evaluate the fault present, where the large volume of data volume needs to be tested during manufacturing and fabrication. Therefore, the challenging fact arises in methodologies to achieve the test data compression. Even though various techniques in the present scenario reduce the testing time, improvement in data volume reduction is still a demanding factor. The proposed scheme aims to obtain a Large Compression Ratio. By using Augmented Recurrence Hopping based Run-Length Coding (ARHRLC) Test Data volume can be reduced and data can be compressed. The proposed ARHRLC coding technique which compares the group code based test vector and it’s duplicate. Data sequence can be decreased in terms volume and area overhead. From the analysis of ISCAS 89 benchmark circuit’s performance shows the proposed coding scheme outperforms the conventional test data compression methods. The Augmented Recurrence Hopping based Run-Length Coding procedure skips the repeated sequence in the test vector group and estimate conversely perfect example of a separate test information section or various test information fragment. The test result demonstrates that the compression proportion and calculation time is lessened.


Circuit under Test (CUT) Augmented Recurrence Hopping based Run-Length Coding (ARHRLC) Run-Length Coding (RLC) Huffman coding (HC) Shifted Alternating Frequency Directed Run-length Coding (SAFDR) 


  1. 1.
    Kavousianos, X., Kalligerous, E., & Nikolos, D. (2007). Optimal selective Huffman coding for test-data compression. IEEE Transactions on Computers, 56(8), 1146–1152.MathSciNetCrossRefGoogle Scholar
  2. 2.
    Wang, Z., & Chakrabarty, K. (2008). Test data compression using selective encoding of scan slices. IEEE Transactions on VLSI Systems, 16(11), 1429–1440.CrossRefGoogle Scholar
  3. 3.
    Gonciari, P. T., Al-Hashimi, B., & Nicolici, N. (2003). Variable-length input Huffman coding for system-on-a-chip test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(6), 783–796.CrossRefGoogle Scholar
  4. 4.
    Raun, X., & Katti, R. (2006). A efficient data-independent technique for compression test vectors in systems-on-a-chip. In Proceedings of IEEE computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Washington, DC 2006, (pp. 153–158).Google Scholar
  5. 5.
    Tehranipoor, M., Nourani, M., & Chakrabarty, K. (2005). Nine-coded compression technique for testing embedded cores in SoCs. IEEE Transactions on VLSI Systems, 13(6), 719–731.CrossRefGoogle Scholar
  6. 6.
    Balakrishnan, K. J., & Touba, N. A. (2007). Relationship between entropy and test data compression. IEEE Transactions on CAD of Integrated Circuits and Systems, 26(2), 386–395.CrossRefGoogle Scholar
  7. 7.
    Lee, L.-J., Tseng, W.-D., Lin, R.-D., Chakrabarty, & Chang, C.-H. (2012). 2n pattern run-length for test data compression. IEEE Transactions on CAD of Integrated circuits and System, 31(4), 644–648.CrossRefGoogle Scholar
  8. 8.
    Yi, M., Liang, H., Zhang, L., & Zhan, W. (2010). A novel X-ploiting strategy for improving performance of test data compression. IEEE Transaction on VLSI System, 18(02), 324–329.CrossRefGoogle Scholar
  9. 9.
    Bernardeschi, C., Cassano, L., Cimino, M. G., & Domenici, A. (2013). GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs. Journal of Systems Architecture, 59(10), 1243–1254.CrossRefGoogle Scholar
  10. 10.
    Kwasnicka, H., & Przewozniczek, M. (2011). Multi population pattern searching algorithm: A new evolutionary method based on the idea of messy genetic algorithm. IEEE Transactions on Evolutionary Computation, 15(5), 715–734.CrossRefGoogle Scholar
  11. 11.
    Jervan, G., Eles, P., Peng, Z., Ubar, R., & Jenihhin, M. (2014). Test time minimization for hybrid BIST of core-based systems. In VLSI test symposium, 2014.Google Scholar
  12. 12.
    Jervan, G., Eles, P., Peng, Z., Ubar, R., & Jenihhin, M. (2014). Hybrid BIST time minimization for core-based systems with STUMPS architecture. In VLSI test symposium, 2014.Google Scholar
  13. 13.
    Garbolino, T., & Papa, G. (2010). Genetic algorithm for test pattern generator design. Applied Intelligence, 32(2), 193–204.CrossRefGoogle Scholar
  14. 14.
    Kavousianos, X., Kalligeros, E., & Nikolos, D. (2007). Multilevel Huffman coding: An efficient test-data compression method for IP cores. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(6), 1070–1083.CrossRefGoogle Scholar
  15. 15.
    Remersaro, S. (2008). On low power test and DFT techniques for test set compaction (Ph.D. dissertation, University of Iowa, 2008).Google Scholar
  16. 16.
    Feng, J., & Li, G. (2008). A test data compression method for system-on-a-chip. In Proceedings of the 4th IEEE international symposium on electronic design, test and applications (DELTA’08), January 2008.Google Scholar
  17. 17.
    Basu, K., & Mishra, P. (2010). Test data compression using efficient bitmask and dictionary selection methods. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(9), 1277–1286.CrossRefGoogle Scholar
  18. 18.
    Mehta, U. S., Dasgupta, K. S., Devashrayee, N. M. (2010). Hamming distance based reordering and column wise bit stuffing with difference vector: a better scheme for test data compression with run length based codes. In 23rd international conference on VLSI design, 2010.Google Scholar
  19. 19.
    Sharma, D., Ghosh, D., & Vohra, H. (2012). Test data volume minimization using double hamming distance reordering with mixed RL-Huffman based compression scheme for system-on-chip. In Nirma University international conference on engineering, NUiCONE-2012 (pp. 06–08), December 2012.Google Scholar
  20. 20.
    Sismanoglou, P., & Nikolos, D. (2013). Input test data compression based on the reuse of parts of dictionary entries: Static and dynamic approaches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(11), 1762–1775.CrossRefGoogle Scholar
  21. 21.
    Sathiyapriya, R.,Yuvasrri Sindhu, M., & Immanuel Rairosario, P. (2013). FPGA implementation of hybrid test data compression method using scan chain compaction and dictionary based scheme. International Journal of Scientific and Research Publications, ISSN 2250-3153, April 2013.Google Scholar
  22. 22.
    Tie-Bin, W., Liu, H.-Z., & Liu, P.-X. (2013). Efficient test compression technique for SoC based on block merging and eight coding. Journal of Electronic Testing: Theory and Applications, 24, 849–859.Google Scholar
  23. 23.
    Chandra, A., & Chakrabarty, K. (2001). Combining low-power scan testing and test data compression for system-on-a-chip. In Design automation conference (pp. 166–169).Google Scholar
  24. 24.
    Zhan, W., & El-Malesh, A. (2012). A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC). In International conference (pp. 21–25).Google Scholar
  25. 25.
    Gonciari, P. T., Rosinger, P., & Al-Hashimi, B. M. (2005). Compression considerations in test access mechanism design. IEE Proceedings - Computers and Digital Techniques, 152(1), 89–96.Google Scholar
  26. 26.
    Starks, M. J., & Lee, M. C. (2000). Matched filtering for the measurement of conjugately ducted VLF transmissions. Radio Science, 35(2), 351–360.Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of ECEMuthayammal Engineering CollegeNamakkalIndia
  2. 2.SNS College of TechnologyCoimbatoreIndia

Personalised recommendations