Floating Point CGRA based Ultra-Low Power DSP Accelerator

Abstract

Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as energy efficient accelerators providing a high grade of flexibility in both academia and industry. However, with the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications. Experimental results show that the proposed accelerator achieves a maximum of 4.61× speedup compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative of wide range of EEG signal processing applications with an area overhead of 1.9×. The proposed CGRA achieves a maximum of 6.5× energy efficiency compared to the single core CPU. While comparing the execution with the multi-core CPU with 8 cores, the proposed CGRA achieves up to 4.4× energy gain.

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Notes

  1. 1.

    In order to maintain a consistency, a single template of PULP-cluster with 8 RI5CY cores has been used to perform all of the experiments in this paper. Pulp-cluster automatically disables other cores not in use.

  2. 2.

    PULP-cluster includes a shared FPU cluster which itself consists of 4 FPUs and PULP-cluster automatically disables the other FPUs not in use.

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Correspondence to Rohit Prasad.

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Prasad, R., Das, S., Martin, K.J.M. et al. Floating Point CGRA based Ultra-Low Power DSP Accelerator. J Sign Process Syst (2021). https://doi.org/10.1007/s11265-020-01630-2

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Keywords

  • CGRA architecture
  • Floating point
  • Ultra-low power
  • DSP acceleration