CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism
- 62 Downloads
Running discrete Fourier transform (running DFT) is being used to overcome the drawbacks of ping pong buffer technique by employing fast Fourier transform (FFT) for real time spectrum analyzer, However, the major drawback of existing MAC or CORDIC (CO-ordinate Rotational DIgital Computer) based computation of running DFT is error accumulation due to finite precision machine and iterative computation which deteriorate the output in long run. Hence, two new alternative CORDIC based architectures with trade-off area and throughput for the computation of running DFT with refreshing mechanism are proposed in this paper to circumvent the problem of error accumulation. The novelty of these two proposed architectures is low hardware complexity or high throughput and provides the spectrum updates on sample-by-sample basis within tolerable error limit. The proposed designs are implemented using verilogHDL and synthesized using commercially available 0.18μ m CMOS technology to estimate its computation performances. The first order hardware complexities of these proposed architectures are compared with existing architectures. The proposed designs in this paper have potential applications for continuous monitoring of Fourier spectrum in the domain of power spectrum analysis, biomedical signal monitoring systems and communication system.
KeywordsRecursive or running DFT VLSI architecture CORDIC Spectrum analysis
We would like to thank Dr. S. Singh, Associate Professor, Department of Humanities and Social Sciences, IIT Patna for her valuable suggestions to improve english grammar of the manuscript.
- 2.Shuenn-Shyang, W., & Chien-Sung, L. (2007). An area-efficient design of variable length fast Fourier transform processor. Journal of Signal Processing Systems, 51(3), 245–256.Google Scholar
- 3.Gautam, V., Ray, KC, Haddow, P. (2011). Hardware efficient design of variable length fft processor. In Proceedings of the IEEE 14th international symposium design and diagnostics of electronic circuits and systems (pp. 309–312).Google Scholar
- 9.Lai, S.-C., Juang, W.-H., Chang, C.-L., Lin, C.-C., Luo, C.-H., Lei, S.-F. (2010). Low-computation-cycle, power-efficient, and reconfigurable design of recursive DFT for portable digital radio mondiale receiver. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(8), 647–651.CrossRefGoogle Scholar
- 12.Varga, L., Kollár, Z., Horváth, P. (2012). Recursive Discrete Fourier Transform based SMT receivers for cognitive radio applications. In Proceedings of the 19th international conference on systems, signals and image processing (pp. 130–133).Google Scholar
- 14.Inggs, M., van der Byl, A., Tong, C. (2013). Commensal radar: Range-Doppler processing using a recursive DFT. In Proceedings of the IEEE international conference on radar (pp. 292–297).Google Scholar
- 25.Villalba, J., Hidalgo, J. A., Zapata, E. L., Antelo, E., Bruguera, J. D. (1995). CORDIC architectures with parallel compensation of the scale factor. In Proceedings on Application Specific Array Processors. Spain, (Vol. 1 pp. 258–269).Google Scholar