Journal of Signal Processing Systems

, Volume 90, Issue 1, pp 29–38 | Cite as

A Modular Architecture for Structured Long Block-Length LDPC Decoders

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Abstract

High-speed, low-area decoders for low-density parity-check (LDPC) codes with long block lengths are challenging to implement due to the large amount of nodes and edges required. In this paper, we implement a decoder for a (32643, 30592) LDPC code that has variable nodes of degree 7, check nodes degrees of 111 and 112, and requiring 228501 edges, making fully-parallel hardware implementation unfeasible. We analyze the structure of this code and describe a method of replacing the complex interconnect with a local, area-efficient version. We develop a modular architecture resulting in a low-complexity partially-parallel decoder architecture based on the offset min-sum algorithm, showing significant advantages compared to traditional implementations of very long block-length decoders. Synthesis in 65 nm CMOS is performed resulting in a clock frequency of 370 MHz and throughputs of 24 Gbps and 47 Gbps with areas of 7.99 mm2 and 10.18 mm2, respectively. With minimal additional hardware cost, this modular design can be upgraded to achieve a throughput of 93 Gbps.

Keywords

LDPC Partially-parallel ITU G.975.1 40 Gb/s Long block-length 

Notes

Acknowledgements

The authors would like to thank C. Condo for his insightful comments.

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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • Andrew J. Wong
    • 1
  • Saied Hemati
    • 2
  • Warren J. Gross
    • 1
  1. 1.Department of Electrical and Computer EngineeringMcGill UniversityMontrealCanada
  2. 2.Department of Electrical and Computer EngineeringUniversity of IdahoMoscowUSA

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